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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rxtx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rxtx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rxtx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.rxtx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.rxtx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
    
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rxtx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
TX_FIFO_SIZE3
TX_FIFO_WORDS8
RX_FIFO_SIZE3
RX_FIFO_WORDS8

 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rxtx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`uart`
72
73
74
75
76
77
78			`txd_pad_out`
79			`txd_pad_out`
80
81
82
83
84			`rxd_pad_in`
85			`rxd_pad_in`
86
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135	133	jt_eaton
136			`elab_verilog`
137			`102.1`
138			`none`
139			`:Simulation:`
140			`./tools/verilog/elab_verilog`
141
142
143			`dest_dir`
144			`io_ports`
145
146
147
148	131	jt_eaton
149
150
151
152	133	jt_eaton
153	131	jt_eaton
154			`gen_verilog_sim`
155			`104.0`
156			`none`
157			`:Simulation:`
158			`./tools/verilog/gen_verilog`
159
160
161			`destination`
162			`top.rxtx.sim`
163
164
165			`dest_dir`
166			`../verilog`
167
168
169
170
171
172			`gen_verilog_syn`
173			`104.0`
174			`none`
175			`:Synthesis:`
176			`./tools/verilog/gen_verilog`
177
178
179			`destination`
180			`top.rxtx.syn`
181
182
183			`dest_dir`
184			`../verilog`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201			`fs-sim`
202
203
204
205			`../verilog/copyright.v`
206			`verilogSourceinclude`
207
208
209
210
211
212			`../verilog/sim/top.rxtx.sim`
213			`verilogSourcemodule`
214
215
216
217
218			`../verilog/top.body.tx`
219			`verilogSourcefragment`
220
221
222
223
224
225			`../verilog/top.sim`
226			`verilogSourcefragment`
227
228
229
230
231
232
233
234
235
236			`fs-syn`
237
238
239
240			`../verilog/copyright.v`
241			`verilogSourceinclude`
242
243
244
245
246
247			`../verilog/syn/top.rxtx.syn`
248			`verilogSourcemodule`
249
250
251
252
253			`../verilog/top.body.tx`
254			`verilogSourcefragment`
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274			`Hierarchical`
275
276
277			`spirit:library="logic"`
278			`spirit:name="uart"`
279			`spirit:version="rxtx.design"/>`
280
281
282
283
284			`verilog`
285
286
287			`spirit:library="Testbench"`
288			`spirit:name="toolflow"`
289			`spirit:version="verilog"/>`
290
291
292
293
294
295
296
297
298			`sim:Simulation:`
299
300			`Verilog`
301
302
303			`fs-sim`
304
305
306
307
308			`syn:Synthesis:`
309
310			`Verilog`
311
312
313			`fs-syn`
314
315
316
317
318
319			`doc`
320
321
322			`spirit:library="Testbench"`
323			`spirit:name="toolflow"`
324			`spirit:version="documentation"/>`
325
326			`:Documentation:`
327			`Verilog`
328
329
330
331
332
333
334
335
336
337
338
339
340
341			`PRESCALE5'b01100`
342			`PRE_SIZE5`
343			`SIZE8`
344			`DIV0`
345			`DIV_SIZE4`
346			`TX_FIFO_SIZE3`
347			`TX_FIFO_WORDS8`
348			`RX_FIFO_SIZE3`
349			`RX_FIFO_WORDS8`
350
351
352
353
354
355
356
357
358			`parity_enable`
359			`wire`
360			`in`
361
362
363			`divider_in`
364			`wire`
365			`in`
366			`DIV_SIZE-10`
367
368
369			`cts_pad_in`
370			`wire`
371			`in`
372
373
374			`rts_pad_out`
375			`reg`
376			`out`
377
378
379
380			`cts_out`
381			`reg`
382			`out`
383
384
385			`rts_in`
386			`wire`
387			`in`
388
389
390			`txd_parity`
391			`wire`
392			`in`
393
394
395			`txd_force_parity`
396			`wire`
397			`in`
398
399
400			`txd_load`
401			`wire`
402			`in`
403
404
405			`txd_break`
406			`wire`
407			`in`
408
409
410			`txd_data_in`
411			`wire`
412			`in`
413			`SIZE-10`
414
415
416			`txd_buffer_empty`
417			`wire`
418			`out`
419
420
421			`rxd_data_avail_stb`
422			`wire`
423			`in`
424
425
426			`rxd_data_avail`
427			`wire`
428			`out`
429
430
431			`rxd_parity`
432			`wire`
433			`in`
434
435
436			`rxd_force_parity`
437			`wire`
438			`in`
439
440
441			`rxd_data_out`
442			`wire`
443			`out`
444			`SIZE-10`
445
446
447			`rxd_parity_error`
448			`wire`
449			`out`
450
451
452			`rxd_stop_error`
453			`wire`
454			`out`
455
456
457
458
459
460
461
462
463
464