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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rxtx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_rxtx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_rxtx
    
  

 
 
 
 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_rxtx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_rxtx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rxtx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rxtx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`uart`
72
73
74
75
76
77
78			`txd_pad_out`
79			`txd_pad_out`
80
81
82
83
84			`rxd_pad_in`
85			`rxd_pad_in`
86
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138			`gen_verilog_sim`
139			`104.0`
140			`none`
141			`:Simulation:`
142			`./tools/verilog/gen_verilog`
143
144
145			`destination`
146	134	jt_eaton	`uart_rxtx`
147	131	jt_eaton
148
149
150
151
152			`gen_verilog_syn`
153			`104.0`
154			`none`
155			`:Synthesis:`
156			`./tools/verilog/gen_verilog`
157
158
159			`destination`
160	134	jt_eaton	`uart_rxtx`
161	131	jt_eaton
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`fs-sim`
178
179
180
181			`../verilog/copyright.v`
182			`verilogSourceinclude`
183
184
185
186
187
188	134	jt_eaton	`../verilog/sim/uart_rxtx`
189	131	jt_eaton	`verilogSourcemodule`
190
191
192
193
194			`../verilog/top.body.tx`
195			`verilogSourcefragment`
196
197
198
199
200
201			`../verilog/top.sim`
202			`verilogSourcefragment`
203
204
205	134	jt_eaton
206			`dest_dir`
207			`../views/sim/`
208			`verilogSourcelibraryDir`
209
210	131	jt_eaton
211
212
213	134	jt_eaton
214	131	jt_eaton
215
216
217
218			`fs-syn`
219
220
221
222			`../verilog/copyright.v`
223			`verilogSourceinclude`
224
225
226
227
228
229	134	jt_eaton	`../verilog/syn/uart_rxtx`
230	131	jt_eaton	`verilogSourcemodule`
231
232
233
234
235			`../verilog/top.body.tx`
236			`verilogSourcefragment`
237
238
239	134	jt_eaton
240			`dest_dir`
241			`../views/syn/`
242			`verilogSourcelibraryDir`
243
244	131	jt_eaton
245	134	jt_eaton
246
247	131	jt_eaton
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263			`Hierarchical`
264
265
266			`spirit:library="logic"`
267			`spirit:name="uart"`
268			`spirit:version="rxtx.design"/>`
269
270
271
272
273			`verilog`
274
275
276			`spirit:library="Testbench"`
277			`spirit:name="toolflow"`
278			`spirit:version="verilog"/>`
279
280
281
282
283
284
285
286
287			`sim:Simulation:`
288
289			`Verilog`
290
291
292			`fs-sim`
293
294
295
296
297			`syn:Synthesis:`
298
299			`Verilog`
300
301
302			`fs-syn`
303
304
305
306
307
308			`doc`
309
310
311			`spirit:library="Testbench"`
312			`spirit:name="toolflow"`
313			`spirit:version="documentation"/>`
314
315			`:Documentation:`
316			`Verilog`
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333			`parity_enable`
334			`wire`
335			`in`
336
337
338			`divider_in`
339			`wire`
340			`in`
341			`DIV_SIZE-10`
342
343
344			`cts_pad_in`
345			`wire`
346			`in`
347
348
349			`rts_pad_out`
350			`reg`
351			`out`
352
353
354
355			`cts_out`
356			`reg`
357			`out`
358
359
360			`rts_in`
361			`wire`
362			`in`
363
364
365			`txd_parity`
366			`wire`
367			`in`
368
369
370			`txd_force_parity`
371			`wire`
372			`in`
373
374
375			`txd_load`
376			`wire`
377			`in`
378
379
380			`txd_break`
381			`wire`
382			`in`
383
384
385			`txd_data_in`
386			`wire`
387			`in`
388			`SIZE-10`
389
390
391			`txd_buffer_empty`
392			`wire`
393			`out`
394
395
396			`rxd_data_avail_stb`
397			`wire`
398			`in`
399
400
401			`rxd_data_avail`
402			`wire`
403			`out`
404
405
406			`rxd_parity`
407			`wire`
408			`in`
409
410
411			`rxd_force_parity`
412			`wire`
413			`in`
414
415
416			`rxd_data_out`
417			`wire`
418			`out`
419			`SIZE-10`
420
421
422			`rxd_parity_error`
423			`wire`
424			`out`
425
426
427			`rxd_stop_error`
428			`wire`
429			`out`
430
431
432
433
434
435
436
437
438
439