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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
tx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 

 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.tx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.tx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="tx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
TX_FIFO_SIZE3
TX_FIFO_WORDS8

 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`tx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94
95
96			`txd_buffer_empty`
97
98
99
100
101
102
103			`NIRQ`
104			`txd_buffer_empty_NIRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117	133	jt_eaton
118			`elab_verilog`
119			`102.1`
120			`none`
121			`:Simulation:`
122			`./tools/verilog/elab_verilog`
123
124
125			`dest_dir`
126			`io_ports`
127
128
129
130	131	jt_eaton
131
132
133
134			`gen_verilog_sim`
135			`104.0`
136			`none`
137			`:Simulation:`
138			`./tools/verilog/gen_verilog`
139
140
141			`destination`
142			`top.tx.sim`
143
144
145			`dest_dir`
146			`../verilog`
147
148
149
150
151
152			`gen_verilog_syn`
153			`104.0`
154			`none`
155			`:Synthesis:`
156			`./tools/verilog/gen_verilog`
157
158
159			`destination`
160			`top.tx.syn`
161
162
163			`dest_dir`
164			`../verilog`
165
166
167
168
169
170
171
172
173
174
175
176
177			`fs-sim`
178
179
180
181			`../verilog/copyright.v`
182			`verilogSourceinclude`
183
184
185
186
187
188			`../verilog/sim/top.tx.sim`
189			`verilogSourcemodule`
190
191
192
193
194			`../verilog/top.body.tx`
195			`verilogSourcefragment`
196
197
198
199
200			`../verilog/top.sim`
201			`verilogSourcefragment`
202
203
204
205
206
207
208
209			`fs-syn`
210
211
212
213			`../verilog/copyright.v`
214			`verilogSourceinclude`
215
216
217
218
219
220			`../verilog/syn/top.tx.syn`
221			`verilogSourcemodule`
222
223
224
225
226			`../verilog/top.body.tx`
227			`verilogSourcefragment`
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248			`Hierarchical`
249
250
251			`spirit:library="logic"`
252			`spirit:name="uart"`
253			`spirit:version="tx.design"/>`
254
255
256
257
258			`verilog`
259
260
261			`spirit:library="Testbench"`
262			`spirit:name="toolflow"`
263			`spirit:version="verilog"/>`
264
265
266
267
268
269
270
271
272
273			`sim:Simulation:`
274
275			`Verilog`
276
277
278			`fs-sim`
279
280
281
282
283			`syn:Synthesis:`
284
285			`Verilog`
286
287
288			`fs-syn`
289
290
291
292
293
294			`doc`
295
296
297			`spirit:library="Testbench"`
298			`spirit:name="toolflow"`
299			`spirit:version="documentation"/>`
300
301			`:Documentation:`
302			`Verilog`
303
304
305
306
307
308
309
310
311
312
313
314
315			`PRESCALE5'b01100`
316			`PRE_SIZE5`
317			`SIZE8`
318			`DIV0`
319			`DIV_SIZE4`
320			`TX_FIFO_SIZE3`
321			`TX_FIFO_WORDS8`
322
323
324
325
326
327
328
329
330			`parity_enable`
331			`wire`
332			`in`
333
334
335			`divider_in`
336			`wire`
337			`in`
338			`DIV_SIZE-10`
339
340
341			`cts_pad_in`
342			`wire`
343			`in`
344
345
346			`rts_pad_out`
347			`reg`
348			`out`
349
350
351
352
353			`cts_out`
354			`reg`
355			`out`
356
357
358			`rts_in`
359			`wire`
360			`in`
361
362
363			`txd_parity`
364			`wire`
365			`in`
366
367
368			`txd_force_parity`
369			`wire`
370			`in`
371
372
373			`txd_load`
374			`wire`
375			`in`
376
377
378			`txd_break`
379			`wire`
380			`in`
381
382
383			`txd_data_in`
384			`wire`
385			`in`
386			`SIZE-10`
387
388
389			`txd_buffer_empty`
390			`wire`
391			`out`
392
393
394			`rxd_data_avail_stb`
395			`wire`
396			`in`
397
398
399			`rxd_data_avail`
400			`wire`
401			`out`
402
403
404			`rxd_parity`
405			`wire`
406			`in`
407
408
409			`rxd_force_parity`
410			`wire`
411			`in`
412
413
414			`rxd_data_out`
415			`wire`
416			`out`
417			`SIZE-10`
418
419
420			`rxd_parity_error`
421			`wire`
422			`out`
423
424
425			`rxd_stop_error`
426			`wire`
427			`out`
428
429
430
431
432
433
434
435
436
437
438