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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
tx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 

 
 

 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_tx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_tx
    
  

 
 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_tx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_tx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="tx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`tx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94
95
96			`txd_buffer_empty`
97
98
99
100
101
102
103			`NIRQ`
104			`txd_buffer_empty_NIRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120			`gen_verilog_sim`
121			`104.0`
122			`none`
123			`:Simulation:`
124			`./tools/verilog/gen_verilog`
125
126
127			`destination`
128	134	jt_eaton	`uart_tx`
129	131	jt_eaton
130
131
132
133
134			`gen_verilog_syn`
135			`104.0`
136			`none`
137			`:Synthesis:`
138			`./tools/verilog/gen_verilog`
139
140
141			`destination`
142	134	jt_eaton	`uart_tx`
143	131	jt_eaton
144
145
146
147
148
149
150
151
152
153
154
155			`fs-sim`
156
157
158
159			`../verilog/copyright.v`
160			`verilogSourceinclude`
161
162
163
164
165
166	134	jt_eaton	`../verilog/sim/uart_tx`
167	131	jt_eaton	`verilogSourcemodule`
168
169
170
171
172			`../verilog/top.body.tx`
173			`verilogSourcefragment`
174
175
176
177
178			`../verilog/top.sim`
179			`verilogSourcefragment`
180
181
182	134	jt_eaton
183			`dest_dir`
184			`../views/sim/`
185			`verilogSourcelibraryDir`
186
187	131	jt_eaton
188
189	134	jt_eaton
190	131	jt_eaton
191
192
193			`fs-syn`
194
195
196
197			`../verilog/copyright.v`
198			`verilogSourceinclude`
199
200
201
202
203
204	134	jt_eaton	`../verilog/syn/uart_tx`
205	131	jt_eaton	`verilogSourcemodule`
206
207
208
209
210			`../verilog/top.body.tx`
211			`verilogSourcefragment`
212
213
214	134	jt_eaton
215			`dest_dir`
216			`../views/syn/`
217			`verilogSourcelibraryDir`
218
219	131	jt_eaton
220	134	jt_eaton
221	131	jt_eaton
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238			`Hierarchical`
239
240
241			`spirit:library="logic"`
242			`spirit:name="uart"`
243			`spirit:version="tx.design"/>`
244
245
246
247
248			`verilog`
249
250
251			`spirit:library="Testbench"`
252			`spirit:name="toolflow"`
253			`spirit:version="verilog"/>`
254
255
256
257
258
259
260
261
262
263			`sim:Simulation:`
264
265			`Verilog`
266
267
268			`fs-sim`
269
270
271
272
273			`syn:Synthesis:`
274
275			`Verilog`
276
277
278			`fs-syn`
279
280
281
282
283
284			`doc`
285
286
287			`spirit:library="Testbench"`
288			`spirit:name="toolflow"`
289			`spirit:version="documentation"/>`
290
291			`:Documentation:`
292			`Verilog`
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308			`parity_enable`
309			`wire`
310			`in`
311
312
313			`divider_in`
314			`wire`
315			`in`
316			`DIV_SIZE-10`
317
318
319			`cts_pad_in`
320			`wire`
321			`in`
322
323
324			`rts_pad_out`
325			`reg`
326			`out`
327
328
329
330
331			`cts_out`
332			`reg`
333			`out`
334
335
336			`rts_in`
337			`wire`
338			`in`
339
340
341			`txd_parity`
342			`wire`
343			`in`
344
345
346			`txd_force_parity`
347			`wire`
348			`in`
349
350
351			`txd_load`
352			`wire`
353			`in`
354
355
356			`txd_break`
357			`wire`
358			`in`
359
360
361			`txd_data_in`
362			`wire`
363			`in`
364			`SIZE-10`
365
366
367			`txd_buffer_empty`
368			`wire`
369			`out`
370
371
372			`rxd_data_avail_stb`
373			`wire`
374			`in`
375
376
377			`rxd_data_avail`
378			`wire`
379			`out`
380
381
382			`rxd_parity`
383			`wire`
384			`in`
385
386
387			`rxd_force_parity`
388			`wire`
389			`in`
390
391
392			`rxd_data_out`
393			`wire`
394			`out`
395			`SIZE-10`
396
397
398			`rxd_parity_error`
399			`wire`
400			`out`
401
402
403			`rxd_stop_error`
404			`wire`
405			`out`
406
407
408
409
410
411
412
413
414
415
416