URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
tx
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
          
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
 uart
  
  
      
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
        
      
 
 
  
 
 
 
 
 
 
 

 
 

 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_tx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_tx
    
  

 
 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_tx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_tx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
 
  
 
              
              Hierarchical
               Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`tx`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79
80	135	jt_eaton	`uart`
81
82
83
84
85
86	131	jt_eaton
87	135	jt_eaton
88			`txd_pad_out`
89			`txd_pad_out`
90
91	131	jt_eaton
92
93	135	jt_eaton
94			`rxd_pad_in`
95			`rxd_pad_in`
96
97	131	jt_eaton
98
99	135	jt_eaton
100	131	jt_eaton
101	135	jt_eaton
102
103
104	131	jt_eaton
105
106	135	jt_eaton
107	131	jt_eaton
108	135	jt_eaton
109	131	jt_eaton
110
111
112
113
114	135	jt_eaton
115	131	jt_eaton
116
117	135	jt_eaton
118	131	jt_eaton
119
120
121	135	jt_eaton
122			`gen_verilog_sim`
123			`104.0`
124			`none`
125			`:Simulation:`
126			`tools/verilog/gen_verilog`
127
128
129			`destination`
130			`uart_tx`
131
132
133
134	131	jt_eaton
135	135	jt_eaton
136			`gen_verilog_syn`
137			`104.0`
138			`none`
139			`:Synthesis:`
140			`tools/verilog/gen_verilog`
141
142
143			`destination`
144			`uart_tx`
145
146
147
148	131	jt_eaton
149
150
151	135	jt_eaton
152	131	jt_eaton
153
154	135	jt_eaton
155	131	jt_eaton
156	135	jt_eaton
157			`fs-sim`
158	131	jt_eaton
159	135	jt_eaton
160
161			`../verilog/copyright.v`
162			`verilogSourceinclude`
163
164	131	jt_eaton
165
166	135	jt_eaton
167
168			`../verilog/sim/uart_tx`
169			`verilogSourcemodule`
170
171	131	jt_eaton
172	135	jt_eaton
173
174			`../verilog/top.body.tx`
175			`verilogSourcefragment`
176
177	131	jt_eaton
178	135	jt_eaton
179
180			`../verilog/top.sim`
181			`verilogSourcefragment`
182
183	131	jt_eaton
184	135	jt_eaton
185			`dest_dir`
186			`../views/sim/`
187			`verilogSourcelibraryDir`
188
189	131	jt_eaton
190
191	134	jt_eaton
192	135	jt_eaton
193	131	jt_eaton
194	135	jt_eaton
195			`fs-syn`
196	131	jt_eaton
197	135	jt_eaton
198
199			`../verilog/copyright.v`
200			`verilogSourceinclude`
201
202	131	jt_eaton
203
204	135	jt_eaton
205
206			`../verilog/syn/uart_tx`
207			`verilogSourcemodule`
208
209	131	jt_eaton
210	135	jt_eaton
211
212			`../verilog/top.body.tx`
213			`verilogSourcefragment`
214
215	131	jt_eaton
216	135	jt_eaton
217			`dest_dir`
218			`../views/syn/`
219			`verilogSourcelibraryDir`
220
221	131	jt_eaton
222	134	jt_eaton
223	135	jt_eaton
224	131	jt_eaton
225
226
227
228
229	135	jt_eaton
230	131	jt_eaton
231
232
233
234
235
236	135	jt_eaton
237	131	jt_eaton
238	135	jt_eaton
239
240			`Hierarchical`
241
242
243
244	131	jt_eaton
245
246	135	jt_eaton
247	131	jt_eaton
248
249
250	135	jt_eaton
251	131	jt_eaton
252	135	jt_eaton
253			`Hierarchical`
254			`Hierarchical`
255
256	131	jt_eaton
257
258	135	jt_eaton
259			`verilog`
260
261
262			`ipxact:library="Testbench"`
263			`ipxact:name="toolflow"`
264			`ipxact:version="verilog"/>`
265
266
267
268
269
270
271
272
273
274			`sim:Simulation:`
275	131	jt_eaton
276	135	jt_eaton	`Verilog`
277
278
279			`fs-sim`
280
281
282	131	jt_eaton
283	135	jt_eaton
284			`syn:Synthesis:`
285	131	jt_eaton
286	135	jt_eaton	`Verilog`
287
288
289			`fs-syn`
290
291
292	131	jt_eaton
293
294	135	jt_eaton
295			`doc`
296
297
298			`ipxact:library="Testbench"`
299			`ipxact:name="toolflow"`
300			`ipxact:version="documentation"/>`
301
302			`:Documentation:`
303			`Verilog`
304
305	131	jt_eaton
306
307	135	jt_eaton
308	131	jt_eaton
309
310
311
312
313
314
315
316	135	jt_eaton
317	131	jt_eaton
318
319	135	jt_eaton	`parity_enable`
320			`wire`
321			`in`
322
323	131	jt_eaton
324	135	jt_eaton	`divider_in`
325			`wire`
326			`in`
327			`DIV_SIZE-10`
328
329	131	jt_eaton
330	135	jt_eaton	`cts_pad_in`
331			`wire`
332			`in`
333
334	131	jt_eaton
335	135	jt_eaton	`rts_pad_out`
336			`reg`
337			`out`
338
339	131	jt_eaton
340
341
342	135	jt_eaton	`cts_out`
343			`reg`
344			`out`
345
346	131	jt_eaton
347	135	jt_eaton	`rts_in`
348			`wire`
349			`in`
350
351	131	jt_eaton
352	135	jt_eaton	`txd_parity`
353			`wire`
354			`in`
355
356	131	jt_eaton
357	135	jt_eaton	`txd_force_parity`
358			`wire`
359			`in`
360
361	131	jt_eaton
362	135	jt_eaton	`txd_load`
363			`wire`
364			`in`
365
366	131	jt_eaton
367	135	jt_eaton	`txd_break`
368			`wire`
369			`in`
370
371	131	jt_eaton
372	135	jt_eaton	`txd_data_in`
373			`wire`
374			`in`
375			`SIZE-10`
376
377	131	jt_eaton
378	135	jt_eaton	`txd_buffer_empty`
379			`wire`
380			`out`
381
382	131	jt_eaton
383	135	jt_eaton	`rxd_data_avail_stb`
384			`wire`
385			`in`
386
387	131	jt_eaton
388	135	jt_eaton	`rxd_data_avail`
389			`wire`
390			`out`
391
392	131	jt_eaton
393	135	jt_eaton	`rxd_parity`
394			`wire`
395			`in`
396
397	131	jt_eaton
398	135	jt_eaton	`rxd_force_parity`
399			`wire`
400			`in`
401
402	131	jt_eaton
403	135	jt_eaton	`rxd_data_out`
404			`wire`
405			`out`
406			`SIZE-10`
407
408	131	jt_eaton
409	135	jt_eaton	`rxd_parity_error`
410			`wire`
411			`out`
412
413	131	jt_eaton
414	135	jt_eaton	`rxd_stop_error`
415			`wire`
416			`out`
417
418	131	jt_eaton
419	135	jt_eaton
420	131	jt_eaton
421	135	jt_eaton
422	131	jt_eaton
423
424
425
426
427	135	jt_eaton

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 135