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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131

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1 131 jt_eaton
 
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assign STOP = 1'b0;
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assign BAD = 1'b0;
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