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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
def_tb
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 

    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
 
       
 
 
 
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`top.tb`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64			`top`
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79			`UART_MODEL_CLKCNT4'hc`
80			`UART_MODEL_SIZE4`
81			`DIVIDER4'b0000`
82
83
84
85
86
87
88
89
90
91
92			`Params`
93
94
95			`spirit:library="logic"`
96			`spirit:name="uart"`
97			`spirit:version="def_dut.params"/>`
98
99
100
101
102
103
104			`Bfm`
105
106			`spirit:library="logic"`
107			`spirit:name="uart"`
108			`spirit:version="bfm.design"/>`
109
110
111
112
113			`icarus`
114
115
116			`spirit:library="Testbench"`
117			`spirit:name="toolflow"`
118			`spirit:version="icarus"/>`
119
120
121
122
123
124
125
126
127			`commoncommon`
128			`Verilog`
129
130
131			`fs-common`
132
133
134
135
136
137
138			`sim:Simulation:`
139			`Verilog`
140
141
142			`fs-sim`
143
144
145
146
147
148
149
150			`lint:Lint:`
151			`Verilog`
152
153
154			`fs-lint`
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175			`fs-common`
176
177
178
179			`../verilog/tb.ext`
180			`verilogSourcefragment`
181
182
183
184
185
186			`fs-sim`
187
188
189
190			`../verilog/common/top.tb`
191			`verilogSourcemodule`
192
193
194
195
196
197
198
199
200			`fs-lint`
201
202
203
204			`../verilog/common/top.tb`
205			`verilogSourcemodule`
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 131