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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
def_tb
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_def_tb
    
  

 
 
 

 
 
 
 

 

    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
 
       
 
 
 
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/common/uart_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/uart_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57	134	jt_eaton	`uart_def_tb`
58	131	jt_eaton
59
60
61
62
63
64
65
66
67
68
69
70
71
72			`UART_MODEL_CLKCNT4'hc`
73			`UART_MODEL_SIZE4`
74			`DIVIDER4'b0000`
75
76
77
78
79
80
81
82
83
84
85			`Params`
86
87
88			`spirit:library="logic"`
89			`spirit:name="uart"`
90			`spirit:version="def_dut.params"/>`
91
92
93
94
95
96
97			`Bfm`
98
99			`spirit:library="logic"`
100			`spirit:name="uart"`
101			`spirit:version="bfm.design"/>`
102
103
104
105
106			`icarus`
107
108
109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="icarus"/>`
112
113
114
115
116
117
118
119
120			`commoncommon`
121			`Verilog`
122
123
124			`fs-common`
125
126
127
128
129
130
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138
139
140
141
142
143			`lint:Lint:`
144			`Verilog`
145
146
147			`fs-lint`
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168			`fs-common`
169
170
171
172			`../verilog/tb.ext`
173			`verilogSourcefragment`
174
175
176
177
178
179			`fs-sim`
180
181
182
183	134	jt_eaton	`../verilog/common/uart_def_tb`
184	131	jt_eaton	`verilogSourcemodule`
185
186
187
188
189
190
191
192
193			`fs-lint`
194
195
196
197	134	jt_eaton	`../verilog/common/uart_def_tb`
198	131	jt_eaton	`verilogSourcemodule`
199
200
201
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_def_tb.xml] - Blame information for rev 134