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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
rx_lint
 
 
 
 

 
       
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="rx_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 
 
 

 
 
 
 
  
 
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/uart_rx_lint
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`rx_lint`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47	135	jt_eaton
48	131	jt_eaton
49
50	135	jt_eaton
51			`Dut`
52
53
54			`ipxact:library="logic"`
55			`ipxact:name="uart"`
56			`ipxact:version="rx_dut.params"/>`
57
58
59	131	jt_eaton
60
61	135	jt_eaton
62			`lint`
63			`:Lint:`
64			`Verilog`
65			`fs-lint`
66
67	131	jt_eaton
68
69	135	jt_eaton
70			`rtl_check`
71
72
73			`ipxact:library="Testbench"`
74			`ipxact:name="toolflow"`
75			`ipxact:version="rtl_check"/>`
76
77
78	131	jt_eaton
79	135	jt_eaton
80	131	jt_eaton
81
82
83
84
85	135	jt_eaton
86	131	jt_eaton
87
88
89
90	135	jt_eaton
91	131	jt_eaton
92
93
94
95
96	135	jt_eaton
97			`fs-lint`
98	131	jt_eaton
99	135	jt_eaton
100
101			`../verilog/lint/uart_rx_lint`
102			`verilogSourcemodule`
103
104	131	jt_eaton
105
106
107	135	jt_eaton
108	131	jt_eaton
109
110
111	135	jt_eaton
112	131	jt_eaton
113
114
115
116
117
118	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_lint.xml] - Blame information for rev 135