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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_lint.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rx_lint
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 

  gen_design
  102.1
  none
  :*Simulation:*
>
  ./tools/verilog/gen_design
    
    
      dest_dir
      io_ports
    
  

 

 
 
 
 

 
       
 
 
              
              Dut
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rx_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 
 
 

 
 
 
 
  
 
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/uart_rx_lint
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rx_lint`
41
42
43	133	jt_eaton
44	131	jt_eaton
45	133	jt_eaton
46			`elab_verilog`
47			`102.1`
48			`none`
49			`:Simulation:`
50			`>`
51			`./tools/verilog/elab_verilog`
52
53
54			`configuration`
55			`default`
56
57
58			`dest_dir`
59			`io_ports`
60
61
62
63	131	jt_eaton
64	133	jt_eaton
65			`gen_design`
66			`102.1`
67			`none`
68			`:Simulation:`
69			`>`
70			`./tools/verilog/gen_design`
71
72
73			`dest_dir`
74			`io_ports`
75
76
77
78	131	jt_eaton
79	133	jt_eaton
80	131	jt_eaton
81	133	jt_eaton
82
83
84	131	jt_eaton
85
86
87
88
89
90			`Dut`
91
92
93			`spirit:library="logic"`
94			`spirit:name="uart"`
95			`spirit:version="rx_dut.params"/>`
96
97
98
99
100
101			`lint`
102			`:Lint:`
103			`Verilog`
104			`fs-lint`
105
106
107
108
109			`rtl_check`
110
111
112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="rtl_check"/>`
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136			`fs-lint`
137
138
139
140			`../verilog/lint/uart_rx_lint`
141			`verilogSourcemodule`
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rx_lint.xml] - Blame information for rev 133