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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rxtx_tb
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.rxtx_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
       
 
 
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rxtx_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
      
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.rxtx_tb
        verilogSourcemodule
      
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.rxtx_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
  
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rxtx_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`top.rxtx_tb`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64			`top`
65
66
67
68
69
70
71
72
73
74
75
76
77			`UART_MODEL_CLKCNT4'hc`
78			`UART_MODEL_SIZE4`
79			`DIVIDER4'b0000`
80
81
82
83
84
85
86
87
88			`Params`
89
90
91			`spirit:library="logic"`
92			`spirit:name="uart"`
93			`spirit:version="rxtx_dut.params"/>`
94
95
96
97
98
99			`Bfm`
100
101			`spirit:library="logic"`
102			`spirit:name="uart"`
103			`spirit:version="bfm.design"/>`
104
105
106
107
108
109			`icarus`
110
111
112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="icarus"/>`
115
116
117
118
119
120
121
122
123			`commoncommon`
124			`Verilog`
125
126
127			`fs-common`
128
129
130
131
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139
140
141
142
143			`lint:Lint:`
144			`Verilog`
145
146
147			`fs-lint`
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-common`
164
165
166
167			`../verilog/tb.ext`
168			`verilogSourcefragment`
169
170
171
172
173
174
175			`fs-sim`
176
177
178
179			`../verilog/common/top.rxtx_tb`
180			`verilogSourcemodule`
181
182
183
184
185
186
187
188			`fs-lint`
189
190
191
192			`../verilog/common/top.rxtx_tb`
193			`verilogSourcemodule`
194
195
196
197
198
199
200
201
202
203
204
205

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_tb.xml] - Blame information for rev 131