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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
tx_tb
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_tx_tb
    
  

 
 
 
 
 

 
 
 
 


    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="tx_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/uart_tx_tb
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/uart_tx_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`tx_tb`
41
42
43
44
45
46
47
48
49
50			`gen_verilog`
51			`104.0`
52			`none`
53			`common`
54			`./tools/verilog/gen_verilog`
55
56
57			`destination`
58	134	jt_eaton	`uart_tx_tb`
59	131	jt_eaton
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74			`UART_MODEL_CLKCNT4'hc`
75			`UART_MODEL_SIZE4`
76			`DIVIDER4'b0000`
77
78
79
80
81
82
83			`Params`
84
85
86			`spirit:library="logic"`
87			`spirit:name="uart"`
88			`spirit:version="tx_dut.params"/>`
89
90
91
92
93
94			`Bfm`
95
96			`spirit:library="logic"`
97			`spirit:name="uart"`
98			`spirit:version="bfm.design"/>`
99
100
101
102
103
104			`icarus`
105
106
107			`spirit:library="Testbench"`
108			`spirit:name="toolflow"`
109			`spirit:version="icarus"/>`
110
111
112
113
114
115
116
117
118			`commoncommon`
119			`Verilog`
120
121
122			`fs-common`
123
124
125
126
127
128			`sim:Simulation:`
129			`Verilog`
130
131
132			`fs-sim`
133
134
135
136
137
138
139			`lint:Lint:`
140			`Verilog`
141
142
143			`fs-lint`
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164			`fs-common`
165
166
167
168			`../verilog/tb.ext`
169			`verilogSourcefragment`
170
171
172
173
174
175
176			`fs-sim`
177
178
179
180	134	jt_eaton	`../verilog/common/uart_tx_tb`
181	131	jt_eaton	`verilogSourcemodule`
182
183
184
185
186
187
188
189
190			`fs-lint`
191
192
193
194	134	jt_eaton	`../verilog/common/uart_tx_tb`
195	131	jt_eaton	`verilogSourcemodule`
196
197
198
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_tb.xml] - Blame information for rev 134