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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
tx_tb
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_tx_tb
    
  

 
 
 
 
 

 
 
 
 


    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="tx_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/uart_tx_tb
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/uart_tx_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`tx_tb`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48
49	135	jt_eaton
50			`gen_verilog`
51			`104.0`
52			`none`
53			`:common:`
54			`tools/verilog/gen_verilog`
55
56
57			`destination`
58			`uart_tx_tb`
59
60
61
62	131	jt_eaton
63
64
65
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72	135	jt_eaton
73
74			`UART_MODEL_CLKCNT4'hc`
75			`UART_MODEL_SIZE4`
76			`DIVIDER4'b0000`
77
78	131	jt_eaton
79
80	135	jt_eaton
81	131	jt_eaton
82	135	jt_eaton
83			`Params`
84
85
86			`ipxact:library="logic"`
87			`ipxact:name="uart"`
88			`ipxact:version="tx_dut.params"/>`
89
90
91	131	jt_eaton
92
93	135	jt_eaton
94			`Bfm`
95
96			`ipxact:library="logic"`
97			`ipxact:name="uart"`
98			`ipxact:version="bfm.design"/>`
99
100	131	jt_eaton
101
102
103	135	jt_eaton
104			`icarus`
105
106
107			`ipxact:library="Testbench"`
108			`ipxact:name="toolflow"`
109			`ipxact:version="icarus"/>`
110
111
112	131	jt_eaton
113
114
115
116
117	135	jt_eaton
118			`common:common:`
119			`Verilog`
120
121
122			`fs-common`
123
124
125	131	jt_eaton
126
127	135	jt_eaton
128			`sim:Simulation:`
129			`Verilog`
130
131
132			`fs-sim`
133
134
135	131	jt_eaton
136
137
138	135	jt_eaton
139			`lint:Lint:`
140			`Verilog`
141
142
143			`fs-lint`
144
145
146	131	jt_eaton
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153
154
155
156
157	135	jt_eaton
158	131	jt_eaton
159
160
161	135	jt_eaton
162	131	jt_eaton
163	135	jt_eaton
164			`fs-common`
165	131	jt_eaton
166	135	jt_eaton
167
168			`../verilog/tb.ext`
169			`verilogSourcefragment`
170
171	131	jt_eaton
172	135	jt_eaton
173	131	jt_eaton
174
175	135	jt_eaton
176			`fs-sim`
177	131	jt_eaton
178	135	jt_eaton
179
180			`../verilog/common/uart_tx_tb`
181			`verilogSourcemodule`
182
183	131	jt_eaton
184
185	135	jt_eaton
186	131	jt_eaton
187
188
189	135	jt_eaton
190			`fs-lint`
191	131	jt_eaton
192	135	jt_eaton
193
194			`../verilog/common/uart_tx_tb`
195			`verilogSourcemodule`
196
197	131	jt_eaton
198
199	135	jt_eaton
200	131	jt_eaton
201
202
203
204	135	jt_eaton
205	131	jt_eaton
206
207
208	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_tb.xml] - Blame information for rev 135