URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [verilog/] [top.body] - Blame information for rev 133

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assign        eppwait_out   =  1'b0;
assign        eppwait_oe    =  1'b0;
assign        usbwr_out     =  1'b0;
assign        usbwr_oe      =  1'b0;
assign        usbmode_out   =  1'b0;
assign        usbmode_oe    =  1'b0;
assign        usboe_out     =  1'b0;
assign        usboe_oe      =  1'b0;
assign        usbadr_out    = 2'b00;
assign        usbadr_oe     =  1'b0;
assign        usbpktend_out =  1'b0;
assign        usbpktend_oe  =  1'b0;
assign        usbdir_out    =  1'b0;
assign        usbdir_oe     =  1'b0;
assign        eppdb_out     = 8'h00;
assign        eppdb_oe      =  1'b0;
assign        usbclk_out    =  1'b0;
assign        usbclk_oe     =  1'b0;
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`assign eppwait_out = 1'b0;`
3			`assign eppwait_oe = 1'b0;`
4			`assign usbwr_out = 1'b0;`
5			`assign usbwr_oe = 1'b0;`
6			`assign usbmode_out = 1'b0;`
7			`assign usbmode_oe = 1'b0;`
8			`assign usboe_out = 1'b0;`
9			`assign usboe_oe = 1'b0;`
10			`assign usbadr_out = 2'b00;`
11			`assign usbadr_oe = 1'b0;`
12			`assign usbpktend_out = 1'b0;`
13			`assign usbpktend_oe = 1'b0;`
14			`assign usbdir_out = 1'b0;`
15			`assign usbdir_oe = 1'b0;`
16			`assign eppdb_out = 8'h00;`
17			`assign eppdb_oe = 1'b0;`
18			`assign usbclk_out = 1'b0;`
19			`assign usbclk_oe = 1'b0;`
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [verilog/] [top.body] - Blame information for rev 133