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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
usb_epp
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="usb_epp"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 
 
eppastb_in
wire
in

 
eppdstb_in
wire
in

 
usbflag_in
wire
in

 
eppwait_out
wire
out

 
eppwait_in
wire
in

 
eppwait_oe
wire
out

 
usbwr_out
wire
out

 
usbwr_oe
wire
out

 
usbwr_in
wire
in

 
usbmode_out
wire
out

 
usbmode_oe
wire
out

 
usbmode_in
wire
in

 
usboe_out
wire
out

 
usboe_oe
wire
out

 
usboe_in
wire
in

 
usbadr_out
wire
out
10

 
usbadr_oe
wire
out

 
usbadr_in
wire
in
10

 
usbpktend_out
wire
out

 
usbpktend_oe
wire
out

 
usbpktend_in
wire
in

 
usbdir_out
wire
out

 
usbdir_oe
wire
out

 
usbdir_in
wire
in

 
eppdb_in
wire
in
70

 
eppdb_out
wire
out
70

 
eppdb_oe
wire
out

 
eppwr_in
wire
in

 
usbclk_out
wire
out

 
usbclk_oe
wire
out

 
usbclk_in
wire
in

 
usbrdy_in
wire
in

 

 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`usb_epp`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81			`gen_verilog`
82			`104.0`
83			`none`
84			`common`
85			`./tools/verilog/gen_verilog`
86
87
88			`destination`
89			`top`
90
91
92			`dest_dir`
93			`../verilog`
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`fs-common`
109
110
111
112			`../verilog/top.body`
113			`verilogSourcefragment`
114
115
116
117
118
119
120
121
122
123
124			`fs-sim`
125
126
127
128			`../verilog/copyright.v`
129			`verilogSourceinclude`
130
131
132
133
134			`../verilog/common/top`
135			`verilogSourcemodule`
136
137
138
139
140
141
142
143
144
145
146			`fs-syn`
147
148
149
150			`../verilog/copyright.v`
151			`verilogSourceinclude`
152
153
154
155
156			`../verilog/common/top`
157			`verilogSourcemodule`
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176			`Hierarchical`
177
178
179			`spirit:library="logic"`
180			`spirit:name="usb_epp"`
181			`spirit:version="def.design"/>`
182
183
184
185
186			`verilog`
187
188
189			`spirit:library="Testbench"`
190			`spirit:name="toolflow"`
191			`spirit:version="verilog"/>`
192
193
194
195
196
197
198
199
200			`commoncommon`
201
202			`Verilog`
203
204
205			`fs-common`
206
207
208
209
210
211
212			`sim:Simulation:`
213
214			`Verilog`
215
216
217			`fs-sim`
218
219
220
221
222			`syn:Synthesis:`
223
224			`Verilog`
225
226
227			`fs-syn`
228
229
230
231
232
233			`doc`
234
235
236			`spirit:library="Testbench"`
237			`spirit:name="toolflow"`
238			`spirit:version="documentation"/>`
239
240			`:Documentation:`
241			`Verilog`
242
243
244
245
246
247
248
249
250
251
252			`eppastb_in`
253			`wire`
254			`in`
255
256
257			`eppdstb_in`
258			`wire`
259			`in`
260
261
262			`usbflag_in`
263			`wire`
264			`in`
265
266
267			`eppwait_out`
268			`wire`
269			`out`
270
271
272			`eppwait_in`
273			`wire`
274			`in`
275
276
277			`eppwait_oe`
278			`wire`
279			`out`
280
281
282			`usbwr_out`
283			`wire`
284			`out`
285
286
287			`usbwr_oe`
288			`wire`
289			`out`
290
291
292			`usbwr_in`
293			`wire`
294			`in`
295
296
297			`usbmode_out`
298			`wire`
299			`out`
300
301
302			`usbmode_oe`
303			`wire`
304			`out`
305
306
307			`usbmode_in`
308			`wire`
309			`in`
310
311
312			`usboe_out`
313			`wire`
314			`out`
315
316
317			`usboe_oe`
318			`wire`
319			`out`
320
321
322			`usboe_in`
323			`wire`
324			`in`
325
326
327			`usbadr_out`
328			`wire`
329			`out`
330			`10`
331
332
333			`usbadr_oe`
334			`wire`
335			`out`
336
337
338			`usbadr_in`
339			`wire`
340			`in`
341			`10`
342
343
344			`usbpktend_out`
345			`wire`
346			`out`
347
348
349			`usbpktend_oe`
350			`wire`
351			`out`
352
353
354			`usbpktend_in`
355			`wire`
356			`in`
357
358
359			`usbdir_out`
360			`wire`
361			`out`
362
363
364			`usbdir_oe`
365			`wire`
366			`out`
367
368
369			`usbdir_in`
370			`wire`
371			`in`
372
373
374			`eppdb_in`
375			`wire`
376			`in`
377			`70`
378
379
380			`eppdb_out`
381			`wire`
382			`out`
383			`70`
384
385
386			`eppdb_oe`
387			`wire`
388			`out`
389
390
391			`eppwr_in`
392			`wire`
393			`in`
394
395
396			`usbclk_out`
397			`wire`
398			`out`
399
400
401			`usbclk_oe`
402			`wire`
403			`out`
404
405
406			`usbclk_in`
407			`wire`
408			`in`
409
410
411			`usbrdy_in`
412			`wire`
413			`in`
414
415
416
417
418
419
420
421
422
423
424
425
426
427