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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
usb_epp
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 
 
eppastb_in
wire
in

 
eppdstb_in
wire
in

 
usbflag_in
wire
in

 
eppwait_out
wire
out

 
eppwait_in
wire
in

 
eppwait_oe
wire
out

 
usbwr_out
wire
out

 
usbwr_oe
wire
out

 
usbwr_in
wire
in

 
usbmode_out
wire
out

 
usbmode_oe
wire
out

 
usbmode_in
wire
in

 
usboe_out
wire
out

 
usboe_oe
wire
out

 
usboe_in
wire
in

 
usbadr_out
wire
out
10

 
usbadr_oe
wire
out

 
usbadr_in
wire
in
10

 
usbpktend_out
wire
out

 
usbpktend_oe
wire
out

 
usbpktend_in
wire
in

 
usbdir_out
wire
out

 
usbdir_oe
wire
out

 
usbdir_in
wire
in

 
eppdb_in
wire
in
70

 
eppdb_out
wire
out
70

 
eppdb_oe
wire
out

 
eppwr_in
wire
in

 
usbclk_out
wire
out

 
usbclk_oe
wire
out

 
usbclk_in
wire
in

 
usbrdy_in
wire
in

 

 
 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`usb_epp`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76
77
78	133	jt_eaton
79			`elab_verilog`
80			`102.1`
81			`none`
82			`:Simulation:`
83			`./tools/verilog/elab_verilog`
84
85
86			`dest_dir`
87			`io_ports`
88
89
90
91	131	jt_eaton
92
93
94			`gen_verilog`
95			`104.0`
96			`none`
97			`common`
98			`./tools/verilog/gen_verilog`
99
100
101			`destination`
102			`top`
103
104
105			`dest_dir`
106			`../verilog`
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121			`fs-common`
122
123
124
125			`../verilog/top.body`
126			`verilogSourcefragment`
127
128
129
130
131
132
133
134
135
136
137			`fs-sim`
138
139
140
141			`../verilog/copyright.v`
142			`verilogSourceinclude`
143
144
145
146
147			`../verilog/common/top`
148			`verilogSourcemodule`
149
150
151
152
153
154
155
156
157
158
159			`fs-syn`
160
161
162
163			`../verilog/copyright.v`
164			`verilogSourceinclude`
165
166
167
168
169			`../verilog/common/top`
170			`verilogSourcemodule`
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`verilog`
190
191
192			`spirit:library="Testbench"`
193			`spirit:name="toolflow"`
194			`spirit:version="verilog"/>`
195
196
197
198
199
200
201
202
203			`commoncommon`
204
205			`Verilog`
206
207
208			`fs-common`
209
210
211
212
213
214
215			`sim:Simulation:`
216
217			`Verilog`
218
219
220			`fs-sim`
221
222
223
224
225			`syn:Synthesis:`
226
227			`Verilog`
228
229
230			`fs-syn`
231
232
233
234
235
236			`doc`
237
238
239			`spirit:library="Testbench"`
240			`spirit:name="toolflow"`
241			`spirit:version="documentation"/>`
242
243			`:Documentation:`
244			`Verilog`
245
246
247
248
249
250
251
252
253
254
255			`eppastb_in`
256			`wire`
257			`in`
258
259
260			`eppdstb_in`
261			`wire`
262			`in`
263
264
265			`usbflag_in`
266			`wire`
267			`in`
268
269
270			`eppwait_out`
271			`wire`
272			`out`
273
274
275			`eppwait_in`
276			`wire`
277			`in`
278
279
280			`eppwait_oe`
281			`wire`
282			`out`
283
284
285			`usbwr_out`
286			`wire`
287			`out`
288
289
290			`usbwr_oe`
291			`wire`
292			`out`
293
294
295			`usbwr_in`
296			`wire`
297			`in`
298
299
300			`usbmode_out`
301			`wire`
302			`out`
303
304
305			`usbmode_oe`
306			`wire`
307			`out`
308
309
310			`usbmode_in`
311			`wire`
312			`in`
313
314
315			`usboe_out`
316			`wire`
317			`out`
318
319
320			`usboe_oe`
321			`wire`
322			`out`
323
324
325			`usboe_in`
326			`wire`
327			`in`
328
329
330			`usbadr_out`
331			`wire`
332			`out`
333			`10`
334
335
336			`usbadr_oe`
337			`wire`
338			`out`
339
340
341			`usbadr_in`
342			`wire`
343			`in`
344			`10`
345
346
347			`usbpktend_out`
348			`wire`
349			`out`
350
351
352			`usbpktend_oe`
353			`wire`
354			`out`
355
356
357			`usbpktend_in`
358			`wire`
359			`in`
360
361
362			`usbdir_out`
363			`wire`
364			`out`
365
366
367			`usbdir_oe`
368			`wire`
369			`out`
370
371
372			`usbdir_in`
373			`wire`
374			`in`
375
376
377			`eppdb_in`
378			`wire`
379			`in`
380			`70`
381
382
383			`eppdb_out`
384			`wire`
385			`out`
386			`70`
387
388
389			`eppdb_oe`
390			`wire`
391			`out`
392
393
394			`eppwr_in`
395			`wire`
396			`in`
397
398
399			`usbclk_out`
400			`wire`
401			`out`
402
403
404			`usbclk_oe`
405			`wire`
406			`out`
407
408
409			`usbclk_in`
410			`wire`
411			`in`
412
413
414			`usbrdy_in`
415			`wire`
416			`in`
417
418
419
420
421
422
423
424
425
426
427
428
429
430