URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
usb_epp
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      usb_epp_def
    
  

 
 
 

 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 
 
eppastb_in
wire
in

 
eppdstb_in
wire
in

 
usbflag_in
wire
in

 
eppwait_out
wire
out

 
eppwait_in
wire
in

 
eppwait_oe
wire
out

 
usbwr_out
wire
out

 
usbwr_oe
wire
out

 
usbwr_in
wire
in

 
usbmode_out
wire
out

 
usbmode_oe
wire
out

 
usbmode_in
wire
in

 
usboe_out
wire
out

 
usboe_oe
wire
out

 
usboe_in
wire
in

 
usbadr_out
wire
out
10

 
usbadr_oe
wire
out

 
usbadr_in
wire
in
10

 
usbpktend_out
wire
out

 
usbpktend_oe
wire
out

 
usbpktend_in
wire
in

 
usbdir_out
wire
out

 
usbdir_oe
wire
out

 
usbdir_in
wire
in

 
eppdb_in
wire
in
70

 
eppdb_out
wire
out
70

 
eppdb_oe
wire
out

 
eppwr_in
wire
in

 
usbclk_out
wire
out

 
usbclk_oe
wire
out

 
usbclk_in
wire
in

 
usbrdy_in
wire
in

 

 
 

 
 
 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/usb_epp_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/usb_epp_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`usb_epp`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75
76	133	jt_eaton
77	131	jt_eaton	`gen_verilog`
78			`104.0`
79			`none`
80			`common`
81			`./tools/verilog/gen_verilog`
82
83
84			`destination`
85	134	jt_eaton	`usb_epp_def`
86	131	jt_eaton
87
88
89
90
91
92
93
94
95
96
97
98
99
100			`verilog`
101
102
103			`spirit:library="Testbench"`
104			`spirit:name="toolflow"`
105			`spirit:version="verilog"/>`
106
107
108
109
110
111
112
113
114			`commoncommon`
115
116			`Verilog`
117
118
119			`fs-common`
120
121
122
123
124
125
126			`sim:Simulation:`
127
128			`Verilog`
129
130
131			`fs-sim`
132
133
134
135
136			`syn:Synthesis:`
137
138			`Verilog`
139
140
141			`fs-syn`
142
143
144
145
146
147			`doc`
148
149
150			`spirit:library="Testbench"`
151			`spirit:name="toolflow"`
152			`spirit:version="documentation"/>`
153
154			`:Documentation:`
155			`Verilog`
156
157
158
159
160
161
162
163
164
165
166			`eppastb_in`
167			`wire`
168			`in`
169
170
171			`eppdstb_in`
172			`wire`
173			`in`
174
175
176			`usbflag_in`
177			`wire`
178			`in`
179
180
181			`eppwait_out`
182			`wire`
183			`out`
184
185
186			`eppwait_in`
187			`wire`
188			`in`
189
190
191			`eppwait_oe`
192			`wire`
193			`out`
194
195
196			`usbwr_out`
197			`wire`
198			`out`
199
200
201			`usbwr_oe`
202			`wire`
203			`out`
204
205
206			`usbwr_in`
207			`wire`
208			`in`
209
210
211			`usbmode_out`
212			`wire`
213			`out`
214
215
216			`usbmode_oe`
217			`wire`
218			`out`
219
220
221			`usbmode_in`
222			`wire`
223			`in`
224
225
226			`usboe_out`
227			`wire`
228			`out`
229
230
231			`usboe_oe`
232			`wire`
233			`out`
234
235
236			`usboe_in`
237			`wire`
238			`in`
239
240
241			`usbadr_out`
242			`wire`
243			`out`
244			`10`
245
246
247			`usbadr_oe`
248			`wire`
249			`out`
250
251
252			`usbadr_in`
253			`wire`
254			`in`
255			`10`
256
257
258			`usbpktend_out`
259			`wire`
260			`out`
261
262
263			`usbpktend_oe`
264			`wire`
265			`out`
266
267
268			`usbpktend_in`
269			`wire`
270			`in`
271
272
273			`usbdir_out`
274			`wire`
275			`out`
276
277
278			`usbdir_oe`
279			`wire`
280			`out`
281
282
283			`usbdir_in`
284			`wire`
285			`in`
286
287
288			`eppdb_in`
289			`wire`
290			`in`
291			`70`
292
293
294			`eppdb_out`
295			`wire`
296			`out`
297			`70`
298
299
300			`eppdb_oe`
301			`wire`
302			`out`
303
304
305			`eppwr_in`
306			`wire`
307			`in`
308
309
310			`usbclk_out`
311			`wire`
312			`out`
313
314
315			`usbclk_oe`
316			`wire`
317			`out`
318
319
320			`usbclk_in`
321			`wire`
322			`in`
323
324
325			`usbrdy_in`
326			`wire`
327			`in`
328
329
330
331
332
333
334
335
336
337
338
339
340	134	jt_eaton
341	131	jt_eaton
342	134	jt_eaton
343			`fs-common`
344
345
346
347			`../verilog/top.body`
348			`verilogSourcefragment`
349
350
351
352
353
354
355
356
357
358
359			`fs-sim`
360
361
362
363			`../verilog/copyright`
364			`verilogSourceinclude`
365
366
367
368
369			`../verilog/common/usb_epp_def`
370			`verilogSourcemodule`
371
372
373
374
375
376			`dest_dir`
377			`../views/sim/`
378			`verilogSourcelibraryDir`
379
380
381
382
383
384
385
386
387
388
389
390			`fs-syn`
391
392
393
394			`../verilog/copyright`
395			`verilogSourceinclude`
396
397
398
399
400			`../verilog/common/usb_epp_def`
401			`verilogSourcemodule`
402
403
404
405
406
407			`dest_dir`
408			`../views/syn/`
409			`verilogSourcelibraryDir`
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426	131	jt_eaton