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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [char_display] - Blame information for rev 134

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Line No. Rev Author Line
1 131 jt_eaton
 
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module `VARIANT`CHAR_DISPLAY
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#(parameter H_ACTIVE=0
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)
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(
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input wire          clk,
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input wire          reset,
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input wire [2:0]    subchar_line,   // the line number within a character block 0-8
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input wire [2:0]    subchar_pixel,  // the pixel number within a character block 0-8
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input wire [7:0]    ascii_code,
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output wire         pixel_on,
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input wire [13:0]   char_read_addr,
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input wire [13:0]   char_write_addr,
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input wire [7:0]    char_write_data,
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input wire [7:0]    char_gen_rom_data,
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input wire          char_write_enable
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 );
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// the character generator block includes the character RAM
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// and the character generator ROM
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`VARIANT`CHAR_GEN
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 CHAR_GEN
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(
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 .clk                ( clk               ),
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 .reset              ( reset             ),  // reset signal
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 .char_write_addr    ( char_write_addr   ),  // write address
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 .char_write_data    ( char_write_data   ),  // write data
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 .char_write_enable  ( char_write_enable ),  // write enable
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 .char_read_addr     ( char_read_addr    ),  // read address of current character
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 .subchar_line       ( subchar_line      ),  // current line of pixels within current character
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 .subchar_pixel      ( subchar_pixel     ),  // current column of pixels withing current character
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 .char_gen_rom_data  ( char_gen_rom_data ),
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 .pixel_on           ( pixel_on          ),
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 .ascii_code         ( ascii_code        )
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);
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endmodule //CHAR_DISPLAY
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