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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [char_gen] - Blame information for rev 131

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module `VARIANT`CHAR_GEN
 
(
 
input wire           clk,
input wire           reset,
input wire [13:0]    char_write_addr,
input wire [7:0]     char_write_data,
input wire           char_write_enable,
input wire [13:0]    char_read_addr,               // character address "0" is upper left character
input wire [2:0]     subchar_line,               // line number within 8 line block
 
input wire [2:0]     subchar_pixel,               // pixel position within 8 pixel block
 
input wire [7:0]     ascii_code,
 
output reg           pixel_on
 
                         );
 
 
 
reg                   latch_data;
reg                   latch_low_data;
reg                   shift_high;
reg                   shift_low;
reg [3:0]             latched_low_char_data;
reg [7:0]             latched_char_data;
 
 
 
wire [10:0]           chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]};
wire [7:0]            char_gen_rom_data;
 
 
 
// instantiate the character generator ROM
 
 
cde_sram_dp  #(
    .ADDR        (11),
    .WIDTH       (8),
    .WORDS       (1152)
  )
char_gen_rom
(
      .clk       ( clk      ),
      .cs        (1'b1              ),
      .waddr     (11'b00000000000 ),
      .raddr     ( chargen_rom_address),
      .wr        (1'b0              ),
      .rd        (1'b1              ),
      .wdata     (8'h00             ),
      .rdata     ( char_gen_rom_data[7:0]  )
  );
 
 
 
 
 
// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM
always @ (posedge clk )begin
               if (reset) begin
                    latch_data <= 1'b0;
                    end
               else if (subchar_pixel == 3'b110) begin
                    latch_data <= 1'b1;
                    end
               else if (subchar_pixel == 3'b111) begin
                    latch_data <= 1'b0;
                    end
               end
 
always @ (posedge clk )begin
               if (reset) begin
                    latch_low_data <= 1'b0;
                    end
               else if (subchar_pixel == 3'b010) begin
                    latch_low_data <= 1'b1;
                    end
               else if (subchar_pixel == 3'b011) begin
                    latch_low_data <= 1'b0;
                    end
               end
 
always @ (posedge clk )begin
               if (reset) begin
                    shift_high <= 1'b1;
                    end
               else if (subchar_pixel == 3'b011) begin
                    shift_high <= 1'b0;
                    end
               else if (subchar_pixel == 3'b111) begin
                    shift_high <= 1'b1;
                    end
               end
 
always @ (posedge clk )begin
               if (reset) begin
                    shift_low <= 1'b0;
                    end
               else if (subchar_pixel == 3'b011) begin
                    shift_low <= 1'b1;
                    end
               else if (subchar_pixel == 3'b111) begin
                    shift_low <= 1'b0;
                    end
               end
 
// serialize the CHARACTER MODE data
always @ (posedge clk ) begin
     if (reset)
           begin
               pixel_on              <= 1'b0;
               latched_low_char_data <= 4'h0;
               latched_char_data     <= 8'h00;
          end
 
     else if (shift_high)
          begin
               pixel_on              <= latched_char_data [7];
               latched_char_data [7] <= latched_char_data [6];
               latched_char_data [6] <= latched_char_data [5];
               latched_char_data [5] <= latched_char_data [4];
               latched_char_data [4] <= latched_char_data [7];
                    if(latch_low_data) begin
                         latched_low_char_data [3:0] <= latched_char_data [3:0];
                         end
                    else begin
                         latched_low_char_data [3:0] <= latched_low_char_data [3:0];
                         end
               end
 
     else if (shift_low)
          begin
               pixel_on                  <= latched_low_char_data [3];
               latched_low_char_data [3] <= latched_low_char_data [2];
               latched_low_char_data [2] <= latched_low_char_data [1];
               latched_low_char_data [1] <= latched_low_char_data [0];
               latched_low_char_data [0] <= latched_low_char_data [3];
               if  (latch_data)   latched_char_data [7:0] <= char_gen_rom_data[7:0];
               else               latched_char_data [7:0] <= latched_char_data [7:0];
          end
      else
          begin
          latched_low_char_data [3:0]  <= latched_low_char_data [3:0];
          latched_char_data [7:0]      <= latched_char_data [7:0];
          pixel_on                     <= pixel_on;
          end
     end
 
endmodule //CHAR_GEN
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`CHAR_GEN
3
4			`(`
5
6			`input wire clk,`
7			`input wire reset,`
8			`input wire [13:0] char_write_addr,`
9			`input wire [7:0] char_write_data,`
10			`input wire char_write_enable,`
11			`input wire [13:0] char_read_addr, // character address "0" is upper left character`
12			`input wire [2:0] subchar_line, // line number within 8 line block`
13
14			`input wire [2:0] subchar_pixel, // pixel position within 8 pixel block`
15
16			`input wire [7:0] ascii_code,`
17
18			`output reg pixel_on`
19
20			`);`
21
22
23
24			`reg latch_data;`
25			`reg latch_low_data;`
26			`reg shift_high;`
27			`reg shift_low;`
28			`reg [3:0] latched_low_char_data;`
29			`reg [7:0] latched_char_data;`
30
31
32
33			`wire [10:0] chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]};`
34			`wire [7:0] char_gen_rom_data;`
35
36
37
38			`// instantiate the character generator ROM`
39
40
41			`cde_sram_dp #(`
42			`.ADDR (11),`
43			`.WIDTH (8),`
44			`.WORDS (1152)`
45			`)`
46			`char_gen_rom`
47			`(`
48			`.clk ( clk ),`
49			`.cs (1'b1 ),`
50			`.waddr (11'b00000000000 ),`
51			`.raddr ( chargen_rom_address),`
52			`.wr (1'b0 ),`
53			`.rd (1'b1 ),`
54			`.wdata (8'h00 ),`
55			`.rdata ( char_gen_rom_data[7:0] )`
56			`);`
57
58
59
60
61
62			`// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM`
63			`always @ (posedge clk )begin`
64			`if (reset) begin`
65			`latch_data <= 1'b0;`
66			`end`
67			`else if (subchar_pixel == 3'b110) begin`
68			`latch_data <= 1'b1;`
69			`end`
70			`else if (subchar_pixel == 3'b111) begin`
71			`latch_data <= 1'b0;`
72			`end`
73			`end`
74
75			`always @ (posedge clk )begin`
76			`if (reset) begin`
77			`latch_low_data <= 1'b0;`
78			`end`
79			`else if (subchar_pixel == 3'b010) begin`
80			`latch_low_data <= 1'b1;`
81			`end`
82			`else if (subchar_pixel == 3'b011) begin`
83			`latch_low_data <= 1'b0;`
84			`end`
85			`end`
86
87			`always @ (posedge clk )begin`
88			`if (reset) begin`
89			`shift_high <= 1'b1;`
90			`end`
91			`else if (subchar_pixel == 3'b011) begin`
92			`shift_high <= 1'b0;`
93			`end`
94			`else if (subchar_pixel == 3'b111) begin`
95			`shift_high <= 1'b1;`
96			`end`
97			`end`
98
99			`always @ (posedge clk )begin`
100			`if (reset) begin`
101			`shift_low <= 1'b0;`
102			`end`
103			`else if (subchar_pixel == 3'b011) begin`
104			`shift_low <= 1'b1;`
105			`end`
106			`else if (subchar_pixel == 3'b111) begin`
107			`shift_low <= 1'b0;`
108			`end`
109			`end`
110
111			`// serialize the CHARACTER MODE data`
112			`always @ (posedge clk ) begin`
113			`if (reset)`
114			`begin`
115			`pixel_on <= 1'b0;`
116			`latched_low_char_data <= 4'h0;`
117			`latched_char_data <= 8'h00;`
118			`end`
119
120			`else if (shift_high)`
121			`begin`
122			`pixel_on <= latched_char_data [7];`
123			`latched_char_data [7] <= latched_char_data [6];`
124			`latched_char_data [6] <= latched_char_data [5];`
125			`latched_char_data [5] <= latched_char_data [4];`
126			`latched_char_data [4] <= latched_char_data [7];`
127			`if(latch_low_data) begin`
128			`latched_low_char_data [3:0] <= latched_char_data [3:0];`
129			`end`
130			`else begin`
131			`latched_low_char_data [3:0] <= latched_low_char_data [3:0];`
132			`end`
133			`end`
134
135			`else if (shift_low)`
136			`begin`
137			`pixel_on <= latched_low_char_data [3];`
138			`latched_low_char_data [3] <= latched_low_char_data [2];`
139			`latched_low_char_data [2] <= latched_low_char_data [1];`
140			`latched_low_char_data [1] <= latched_low_char_data [0];`
141			`latched_low_char_data [0] <= latched_low_char_data [3];`
142			`if (latch_data) latched_char_data [7:0] <= char_gen_rom_data[7:0];`
143			`else latched_char_data [7:0] <= latched_char_data [7:0];`
144			`end`
145			`else`
146			`begin`
147			`latched_low_char_data [3:0] <= latched_low_char_data [3:0];`
148			`latched_char_data [7:0] <= latched_char_data [7:0];`
149			`pixel_on <= pixel_on;`
150			`end`
151			`end`
152
153			`endmodule //CHAR_GEN`
154

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [char_gen] - Blame information for rev 131