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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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assign  ascii_load          =   1'b0;
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assign  add_l_load          =   1'b0;
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assign  add_h_load          =   1'b0;
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assign  char_color          =   8'h92;
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assign  back_color          =   8'h00;
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assign  cursor_color        =   8'hff;
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assign  wdata               =   8'h00;
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assign STOP = 1'b0;
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assign BAD = 1'b0;
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