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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
vga_char_ctrl
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 

 
 
 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="vga_char_ctrl"
                                   spirit:version="def_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="vga_char_ctrl"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`vga_char_ctrl`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60			`top.tb`
61
62
63			`dest_dir`
64			`../verilog`
65
66
67			`top`
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89			`Params`
90
91
92			`spirit:library="logic"`
93			`spirit:name="vga_char_ctrl"`
94			`spirit:version="def_dut.params"/>`
95
96
97
98
99
100			`Bfm`
101
102			`spirit:library="logic"`
103			`spirit:name="vga_char_ctrl"`
104			`spirit:version="bfm.design"/>`
105
106
107
108
109
110			`icarus`
111
112
113			`spirit:library="Testbench"`
114			`spirit:name="toolflow"`
115			`spirit:version="icarus"/>`
116
117
118
119
120
121
122
123
124			`commoncommon`
125			`Verilog`
126
127
128			`fs-common`
129
130
131
132
133
134			`sim:Simulation:`
135			`Verilog`
136
137
138			`fs-sim`
139
140
141
142
143
144
145			`lint:Lint:`
146			`Verilog`
147
148
149			`fs-lint`
150
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-common`
164
165
166
167			`../verilog/sram.load`
168			`verilogSourcefragment`
169
170
171
172
173
174			`../verilog/tb.ext`
175			`verilogSourcefragment`
176
177
178
179
180
181
182
183
184
185			`fs-sim`
186
187
188
189			`../verilog/common/top.tb`
190			`verilogSourcemodule`
191
192
193
194
195
196
197
198
199
200			`fs-lint`
201
202
203
204			`../verilog/common/top.tb`
205			`verilogSourcemodule`
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
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222

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 131