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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
vga_char_ctrl
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      vga_char_ctrl_def_tb
    
  

 
 
 

 
 
 
 
 
 
 

 
 
 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="vga_char_ctrl"
                                   spirit:version="def_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="vga_char_ctrl"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/vga_char_ctrl_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/vga_char_ctrl_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`vga_char_ctrl`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60	134	jt_eaton	`vga_char_ctrl_def_tb`
61	131	jt_eaton
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`Params`
83
84
85			`spirit:library="logic"`
86			`spirit:name="vga_char_ctrl"`
87			`spirit:version="def_dut.params"/>`
88
89
90
91
92
93			`Bfm`
94
95			`spirit:library="logic"`
96			`spirit:name="vga_char_ctrl"`
97			`spirit:version="bfm.design"/>`
98
99
100
101
102
103			`icarus`
104
105
106			`spirit:library="Testbench"`
107			`spirit:name="toolflow"`
108			`spirit:version="icarus"/>`
109
110
111
112
113
114
115
116
117			`commoncommon`
118			`Verilog`
119
120
121			`fs-common`
122
123
124
125
126
127			`sim:Simulation:`
128			`Verilog`
129
130
131			`fs-sim`
132
133
134
135
136
137
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145
146
147
148
149
150
151
152
153
154
155
156			`fs-common`
157
158
159
160			`../verilog/sram.load`
161			`verilogSourcefragment`
162
163
164
165
166
167			`../verilog/tb.ext`
168			`verilogSourcefragment`
169
170
171
172
173
174
175
176
177
178			`fs-sim`
179
180
181
182	134	jt_eaton	`../verilog/common/vga_char_ctrl_def_tb`
183	131	jt_eaton	`verilogSourcemodule`
184
185
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187
188
189
190
191
192
193			`fs-lint`
194
195
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197	134	jt_eaton	`../verilog/common/vga_char_ctrl_def_tb`
198	131	jt_eaton	`verilogSourcemodule`
199
200
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 134