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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [wb_b.2.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb
b.2
true
true

    CLOCK
    RESET
    ENABLE

Wishbone Soc Interconnect Bus version B.2

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb`
40			`b.2`
41			`true`
42			`true`
43
44			`CLOCK`
45			`RESET`
46			`ENABLE`
47
48			`Wishbone Soc Interconnect Bus version B.2`
49
50	131	jt_eaton
51

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [wb_b.2.xml] - Blame information for rev 135