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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sch/] [model_master.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20100214 1`
2			`C 1700 300 1 0 0 in_port_vector.sym`
3			`{`
4			`T 1700 300 5 10 1 1 0 6 1 1`
5			`refdes=din[dwidth-1:0]`
6			`}`
7			`C 1700 700 1 0 0 in_port.sym`
8			`{`
9			`T 1700 700 5 10 1 1 0 6 1 1`
10			`refdes=rty`
11			`}`
12			`C 1700 1100 1 0 0 in_port.sym`
13			`{`
14			`T 1700 1100 5 10 1 1 0 6 1 1`
15			`refdes=reset`
16			`}`
17			`C 1700 1500 1 0 0 in_port.sym`
18			`{`
19			`T 1700 1500 5 10 1 1 0 6 1 1`
20			`refdes=err`
21			`}`
22			`C 1700 1900 1 0 0 in_port.sym`
23			`{`
24			`T 1700 1900 5 10 1 1 0 6 1 1`
25			`refdes=clk`
26			`}`
27			`C 1700 2300 1 0 0 in_port.sym`
28			`{`
29			`T 1700 2300 5 10 1 1 0 6 1 1`
30			`refdes=ack`
31			`}`
32			`C 4700 300 1 0 0 out_port_vector.sym`
33			`{`
34			`T 5700 300 5 10 1 1 0 0 1 1`
35			`refdes=sel[dwidth/8-1:0]`
36			`}`
37			`C 4700 700 1 0 0 out_port_vector.sym`
38			`{`
39			`T 5700 700 5 10 1 1 0 0 1 1`
40			`refdes=dout[dwidth-1:0]`
41			`}`
42			`C 4700 1100 1 0 0 out_port_vector.sym`
43			`{`
44			`T 5700 1100 5 10 1 1 0 0 1 1`
45			`refdes=adr[awidth-1:0]`
46			`}`
47			`C 4700 1500 1 0 0 out_port.sym`
48			`{`
49			`T 5700 1500 5 10 1 1 0 0 1 1`
50			`refdes=we`
51			`}`
52			`C 4700 1900 1 0 0 out_port.sym`
53			`{`
54			`T 5700 1900 5 10 1 1 0 0 1 1`
55			`refdes=stb`
56			`}`
57			`C 4700 2300 1 0 0 out_port.sym`
58			`{`
59			`T 5700 2300 5 10 1 1 0 0 1 1`
60			`refdes=cyc`
61			`}`