URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sch/] [wb_memory_def.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20100214 1`
2			`C 2600 300 1 0 0 in_port_vector.sym`
3			`{`
4			`T 2600 300 5 10 1 1 0 6 1 1`
5			`refdes=sel_i[wb_byte_lanes-1:0]`
6			`}`
7			`C 2600 700 1 0 0 in_port_vector.sym`
8			`{`
9			`T 2600 700 5 10 1 1 0 6 1 1`
10			`refdes=dat_i[wb_data_width-1:0]`
11			`}`
12			`C 2600 1100 1 0 0 in_port_vector.sym`
13			`{`
14			`T 2600 1100 5 10 1 1 0 6 1 1`
15			`refdes=adr_i[wb_addr_width-1:0]`
16			`}`
17			`C 2600 1500 1 0 0 in_port.sym`
18			`{`
19			`T 2600 1500 5 10 1 1 0 6 1 1`
20			`refdes=we_i`
21			`}`
22			`C 2600 1900 1 0 0 in_port.sym`
23			`{`
24			`T 2600 1900 5 10 1 1 0 6 1 1`
25			`refdes=stb_i`
26			`}`
27			`C 2600 2300 1 0 0 in_port.sym`
28			`{`
29			`T 2600 2300 5 10 1 1 0 6 1 1`
30			`refdes=rst_i`
31			`}`
32			`C 2600 2700 1 0 0 in_port.sym`
33			`{`
34			`T 2600 2700 5 10 1 1 0 6 1 1`
35			`refdes=cyc_i`
36			`}`
37			`C 2600 3100 1 0 0 in_port.sym`
38			`{`
39			`T 2600 3100 5 10 1 1 0 6 1 1`
40			`refdes=clk_i`
41			`}`
42			`C 6300 300 1 0 0 out_port_vector.sym`
43			`{`
44			`T 7300 300 5 10 1 1 0 0 1 1`
45			`refdes=dat_o[wb_data_width-1:0]`
46			`}`
47			`C 6300 700 1 0 0 out_port.sym`
48			`{`
49			`T 7300 700 5 10 1 1 0 0 1 1`
50			`refdes=ack_o`
51			`}`