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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sym/] [model_master.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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B 300 0  3600 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 1650   5 10 1 1 0 0 1 1
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device=model_master
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T 400 1850 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 2000    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 2000    0 10 0 1 0 0 1 1
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library=wishbone
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T 400 2000    0 10 0 1 0 0 1 1
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component=model
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T 400 2000    0 10 0 1 0 0 1 1
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version=master
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=din[dwidth-1:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 4 0 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=rty
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 4 0 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=reset
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 4 0 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=err
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 4 0 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=clk
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
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P 300 1200 0 1200 4 0 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=ack
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
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P 3900 200 4200 200 10 1 1
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{
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T 3800 200 5  10 1 1 0 7 1 1
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pinnumber=sel[dwidth/8-1:0]
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T 3800 200 5  10 0 1 0 7 1 1
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pinseq=7
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}
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P 3900 400 4200 400 10 1 1
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{
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T 3800 400 5  10 1 1 0 7 1 1
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pinnumber=dout[dwidth-1:0]
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T 3800 400 5  10 0 1 0 7 1 1
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pinseq=8
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}
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P 3900 600 4200 600 10 1 1
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{
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T 3800 600 5  10 1 1 0 7 1 1
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pinnumber=adr[awidth-1:0]
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T 3800 600 5  10 0 1 0 7 1 1
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pinseq=9
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}
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P 3900 800 4200 800 4 0 1
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{
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T 3800 800 5  10 1 1 0 7 1 1
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pinnumber=we
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T 3900 800 5  10 0 1 0 7 1 1
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pinseq=10
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}
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P 3900 1000 4200 1000 4 0 1
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{
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T 3800 1000 5  10 1 1 0 7 1 1
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pinnumber=stb
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T 3900 1000 5  10 0 1 0 7 1 1
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pinseq=11
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}
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P 3900 1200 4200 1200 4 0 1
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{
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T 3800 1200 5  10 1 1 0 7 1 1
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pinnumber=cyc
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T 3900 1200 5  10 0 1 0 7 1 1
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pinseq=12
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}

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