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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sym/] [wb_uart16550_bus16_lit.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  3200 2900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 3050   5 10 1 1 0 0 1 1
4 
device=wb_uart16550_bus16_lit
5 
T 400 3250 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 3400    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 3400    0 10 0 1 0 0 1 1
10 
library=wishbone
11 
T 400 3400    0 10 0 1 0 0 1 1
12 
component=wb_uart16550
13 
T 400 3400    0 10 0 1 0 0 1 1
14 
version=bus16_lit
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=wb_sel_i[1:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 10 1 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=wb_dat_i[15:0]
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 10 1 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=wb_adr_i[7:1]
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 4 0 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=wb_we_i
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 4 0 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=wb_stb_i
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=wb_rst_i
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=wb_cyc_i
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
67 
pinnumber=wb_clk_i
68 
T 400 1600 5 10 0 1 0 1 1 1
69 
pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
72 
{
73 
T 400 1800 5 10 1 1 0 1 1 1
74 
pinnumber=srx_pad_i
75 
T 400 1800 5 10 0 1 0 1 1 1
76 
pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
79 
{
80 
T 400 2000 5 10 1 1 0 1 1 1
81 
pinnumber=ri_pad_i
82 
T 400 2000 5 10 0 1 0 1 1 1
83 
pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
86 
{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=dsr_pad_i
89 
T 400 2200 5 10 0 1 0 1 1 1
90 
pinseq=11
91 
}
92 
P 300 2400 0 2400 4 0 1
93 
{
94 
T 400 2400 5 10 1 1 0 1 1 1
95 
pinnumber=dcd_pad_i
96 
T 400 2400 5 10 0 1 0 1 1 1
97 
pinseq=12
98 
}
99 
P 300 2600 0 2600 4 0 1
100 
{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=cts_pad_i
103 
T 400 2600 5 10 0 1 0 1 1 1
104 
pinseq=13
105 
}
106 
P 3500 200 3800 200 10 1 1
107 
{
108 
T 3400 200 5  10 1 1 0 7 1 1
109 
pinnumber=wb_dat_o[15:0]
110 
T 3400 200 5  10 0 1 0 7 1 1
111 
pinseq=14
112 
}
113 
P 3500 400 3800 400 4 0 1
114 
{
115 
T 3400 400 5  10 1 1 0 7 1 1
116 
pinnumber=wb_ack_o
117 
T 3500 400 5  10 0 1 0 7 1 1
118 
pinseq=15
119 
}
120 
P 3500 600 3800 600 4 0 1
121 
{
122 
T 3400 600 5  10 1 1 0 7 1 1
123 
pinnumber=stx_pad_o
124 
T 3500 600 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 3500 800 3800 800 4 0 1
128 
{
129 
T 3400 800 5  10 1 1 0 7 1 1
130 
pinnumber=rts_pad_o
131 
T 3500 800 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 3500 1000 3800 1000 4 0 1
135 
{
136 
T 3400 1000 5  10 1 1 0 7 1 1
137 
pinnumber=int_o
138 
T 3500 1000 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 3500 1200 3800 1200 4 0 1
142 
{
143 
T 3400 1200 5  10 1 1 0 7 1 1
144 
pinnumber=dtr_pad_o
145 
T 3500 1200 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 3500 1400 3800 1400 4 0 1
149 
{
150 
T 3400 1400 5  10 1 1 0 7 1 1
151 
pinnumber=baud_o
152 
T 3500 1400 5  10 0 1 0 7 1 1
153 
pinseq=20
154 
}

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