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  // Internal signals
  reg    [dwidth   -1:0] q;
always@(posedge clk)
  if(reset)
    begin
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b0;
      stb  <= 1'b0;
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
    end
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2			`// Internal signals`
3			`reg [dwidth -1:0] q;`
4			`always@(posedge clk)`
5			`if(reset)`
6			`begin`
7			`adr <= {awidth{1'b0}};`
8			`dout <= {dwidth{1'b0}};`
9			`cyc <= 1'b0;`
10			`stb <= 1'b0;`
11			`we <= 1'h0;`
12			`sel <= {dwidth/8{1'b0}};`
13			`end`
14
15
16

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [master] - Blame information for rev 134