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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [master.tasks] - Blame information for rev 135

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task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);
endtask
 
 
 
 
 
  // Wishbone write cycle
  task wb_write;
    input [awidth -1:0] a;
    input [(dwidth/8) -1:0] s;
    input [dwidth -1:0] d;
    begin
      $display("%t %m cycle %h %h",$realtime,a,d );
      // assert wishbone signal
      adr  <= a;
      dout <= d;
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b1;
      sel  <= s;
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
    end
  endtask
  // Wishbone read cycle
  task wb_read;
    input   [awidth -1:0]  a;
    output  [dwidth -1:0]  d;
    begin
      // assert wishbone signals
      adr  <= a;
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b0;
      sel  <= {dwidth/8{1'b1}};
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      $display("%t %m  cycle %h %h",$realtime,a,din );
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
      d    <= din;
    end
  endtask
  // Wishbone compare cycle (read data from location and compare with expected data)
  task wb_cmp;
    input  [awidth-1:0] a;
    input [(dwidth/8) -1:0] s;
    input  [dwidth-1:0] d_exp;
     begin
      // assert wishbone signals
       adr  <= a;
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b0;
      sel  <= s;
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      $display("%t %m   check %h %h %h",$realtime,a,din,d_exp );
      if (!(d_exp === din))  cg.fail(" Data compare error");
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
   end
  endtask
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`task automatic next;`
2			`input [31:0] num;`
3			`repeat (num) @ (posedge clk);`
4			`endtask`
5
6
7
8
9
10			`// Wishbone write cycle`
11			`task wb_write;`
12			`input [awidth -1:0] a;`
13			`input [(dwidth/8) -1:0] s;`
14			`input [dwidth -1:0] d;`
15			`begin`
16			`$display("%t %m cycle %h %h",$realtime,a,d );`
17			`// assert wishbone signal`
18			`adr <= a;`
19			`dout <= d;`
20			`cyc <= 1'b1;`
21			`stb <= 1'b1;`
22			`we <= 1'b1;`
23			`sel <= s;`
24			`next(1);`
25			`// wait for acknowledge from slave`
26			`while(~ack) next(1);`
27			`// negate wishbone signals`
28			`cyc <= 1'b0;`
29			`stb <= 1'b0;`
30			`adr <= {awidth{1'b0}};`
31			`dout <= {dwidth{1'b0}};`
32			`we <= 1'h0;`
33			`sel <= {dwidth/8{1'b0}};`
34			`end`
35			`endtask`
36			`// Wishbone read cycle`
37			`task wb_read;`
38			`input [awidth -1:0] a;`
39			`output [dwidth -1:0] d;`
40			`begin`
41			`// assert wishbone signals`
42			`adr <= a;`
43			`dout <= {dwidth{1'b0}};`
44			`cyc <= 1'b1;`
45			`stb <= 1'b1;`
46			`we <= 1'b0;`
47			`sel <= {dwidth/8{1'b1}};`
48			`next(1);`
49			`// wait for acknowledge from slave`
50			`while(~ack) next(1);`
51			`$display("%t %m cycle %h %h",$realtime,a,din );`
52			`// negate wishbone signals`
53			`cyc <= 1'b0;`
54			`stb <= 1'b0;`
55			`adr <= {awidth{1'b0}};`
56			`dout <= {dwidth{1'b0}};`
57			`we <= 1'h0;`
58			`sel <= {dwidth/8{1'b0}};`
59			`d <= din;`
60			`end`
61			`endtask`
62			`// Wishbone compare cycle (read data from location and compare with expected data)`
63			`task wb_cmp;`
64			`input [awidth-1:0] a;`
65			`input [(dwidth/8) -1:0] s;`
66			`input [dwidth-1:0] d_exp;`
67			`begin`
68			`// assert wishbone signals`
69			`adr <= a;`
70			`dout <= {dwidth{1'b0}};`
71			`cyc <= 1'b1;`
72			`stb <= 1'b1;`
73			`we <= 1'b0;`
74			`sel <= s;`
75			`next(1);`
76			`// wait for acknowledge from slave`
77			`while(~ack) next(1);`
78			`$display("%t %m check %h %h %h",$realtime,a,din,d_exp );`
79			`if (!(d_exp === din)) cg.fail(" Data compare error");`
80			`// negate wishbone signals`
81			`cyc <= 1'b0;`
82			`stb <= 1'b0;`
83			`adr <= {awidth{1'b0}};`
84			`dout <= {dwidth{1'b0}};`
85			`we <= 1'h0;`
86			`sel <= {dwidth/8{1'b0}};`
87			`end`
88			`endtask`
89
90

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [master.tasks] - Blame information for rev 135