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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  wb_master_model                                             ////

////                                                              ////

////  This file is part of the SPI IP core project                ////

////  http://www.opencores.org/projects/spi/                      ////

////                                                              ////

////  Author(s):                                                  ////

////      - Simon Srot (simons@opencores.org)                     ////

////                                                              ////

////  Based on:                                                   ////

////      - i2c/bench/verilog/wb_master_model.v                   ////

////        Copyright (C) 2001 Richard Herveille                  ////

////                                                              ////

////  All additional information is avaliable in the Readme.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2002 Authors                                   ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module model_master

#( parameter dwidth = 32,

   parameter awidth = 32

 )(

  input wire                  clk,

  input wire                  reset,

  output reg [awidth   -1:0]  adr,

  output reg [dwidth   -1:0]  dout,

  output reg                  cyc,

  output reg                  stb,

  output reg                  we,

  output reg [dwidth/8 -1:0]  sel,

  input  wire [dwidth   -1:0] din,

  input  wire                 ack,

  input  wire                 err,

  input  wire                 rty

);

task automatic next;

  input [31:0] num;

  repeat (num)       @ (posedge clk);

endtask

  // Internal signals

  reg    [dwidth   -1:0] q;

always@(posedge clk)

  if(reset)

    begin

      adr  <= {awidth{1'b0}};

      dout <= {dwidth{1'b0}};

      cyc  <= 1'b0;

      stb  <= 1'b0;

      we   <= 1'h0;

      sel  <= {dwidth/8{1'b0}};

    end

  // Wishbone write cycle

  task wb_write;

    input [awidth -1:0] a;

    input [(dwidth/8) -1:0] s;

    input [dwidth -1:0] d;

    begin

      $display("%t %m cycle %h %h",$realtime,a,d );

      // assert wishbone signal

      adr  <= a;

      dout <= d;

      cyc  <= 1'b1;

      stb  <= 1'b1;

      we   <= 1'b1;

      sel  <= s;

      next(1);

      // wait for acknowledge from slave

      while(~ack) next(1);

      // negate wishbone signals

      cyc  <= 1'b0;

      stb  <= 1'b0;

      adr  <= {awidth{1'b0}};

      dout <= {dwidth{1'b0}};

      we   <= 1'h0;

      sel  <= {dwidth/8{1'b0}};

    end

  endtask

  // Wishbone read cycle

  task wb_read;

    input   [awidth -1:0]  a;

    output  [dwidth -1:0]  d;

    begin

      // assert wishbone signals

      adr  <= a;

      dout <= {dwidth{1'b0}};

      cyc  <= 1'b1;

      stb  <= 1'b1;

      we   <= 1'b0;

      sel  <= {dwidth/8{1'b1}};

      next(1);

      // wait for acknowledge from slave

      while(~ack) next(1);

      $display("%t %m  cycle %h %h",$realtime,a,din );

      // negate wishbone signals

      cyc  <= 1'b0;

      stb  <= 1'b0;

      adr  <= {awidth{1'b0}};

      dout <= {dwidth{1'b0}};

      we   <= 1'h0;

      sel  <= {dwidth/8{1'b0}};

      d    <= din;

    end

  endtask

  // Wishbone compare cycle (read data from location and compare with expected data)

  task wb_cmp;

    input  [awidth-1:0] a;

    input [(dwidth/8) -1:0] s;

    input  [dwidth-1:0] d_exp;

     begin

      // assert wishbone signals

       adr  <= a;

      dout <= {dwidth{1'b0}};

      cyc  <= 1'b1;

      stb  <= 1'b1;

      we   <= 1'b0;

      sel  <= s;

      next(1);

      // wait for acknowledge from slave

      while(~ack) next(1);

      $display("%t %m   check %h %h %h",$realtime,a,din,d_exp );

      if (!(d_exp === din))  cg.fail(" Data compare error");

      // negate wishbone signals

      cyc  <= 1'b0;

      stb  <= 1'b0;

      adr  <= {awidth{1'b0}};

      dout <= {dwidth{1'b0}};

      we   <= 1'h0;

      sel  <= {dwidth/8{1'b0}};

   end

  endtask

endmodule