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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [model_monitor.v] - Blame information for rev 131

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's simulation monitor                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  wishbone protocal  monitor                                  ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module model_monitor
#(parameter TEST_NAME="unspecified",
  parameter INSTANCE="none",
  parameter ADD_WIDTH=32,
  parameter DATA_WIDTH=32
)
(
input wire                   clk,
input wire                   reset,
input wire [ADD_WIDTH-1:0]   wb_adr,
input wire                   wb_ack,
input wire                   wb_err,
input wire                   wb_cyc,
input wire                   wb_stb,
input wire                   wb_we,
input wire [DATA_WIDTH-1:0]  wb_read,
input wire [DATA_WIDTH-1:0]  wb_write,
input wire [3:0]             wb_sel
);
integer    fgeneral;
   //
   // Initialization
   //
   initial
      begin
      fgeneral = $fopen({TEST_NAME,"_",INSTANCE,"_wishbone.log"});
      end
   always @(posedge clk)
     begin
     if (wb_stb && wb_cyc && wb_ack)
           begin
           $fdisplay(fgeneral, "%t  %m WB access  %x %x  %x  %x  %x",  $realtime,   wb_adr, wb_we, wb_sel, wb_read, wb_write,  );
           end
     end
   integer wb_progress;
   reg [ADD_WIDTH-1:0] wb_progress_addr;
   //
   // WISHBONE bus checker
   //
   always @(posedge clk)
     if (reset)
        begin
        wb_progress = 0;
        wb_progress_addr = wb_adr;
        end
     else
       begin
        if (wb_cyc && (wb_progress != 2))
           begin
           wb_progress = 1;
           end
        if (wb_stb)
           begin
           if (wb_progress >= 1)
              begin
              if (wb_progress == 1)      wb_progress_addr = wb_adr;
              wb_progress = 2;
              end
           else
              begin
              $fdisplay(fgeneral, "%t  %m WISHBONE protocol violation: wb_stb_i raised without wb_cyc_i", $realtime);
              end
           end
        if (wb_ack & wb_err)
           begin
           $fdisplay(fgeneral, "%t  %m WISHBONE protocol violation: wb_ack_i and wb_err_i raised at the same time", $realtime);
           end
        if ((wb_progress == 2) && (wb_progress_addr != wb_adr))
           begin
           $fdisplay(fgeneral, "%t  %m WISHBONE protocol violation: wb_adr changed while waiting for wb_err_i/wb_ack_i", $realtime);
           end
        if (wb_ack | wb_err)
           if (wb_progress == 2)
               begin
               wb_progress = 0;
               wb_progress_addr = wb_adr;
               end
           else
             begin
             $fdisplay(fgeneral, "%t  %m WISHBONE protocol violation: wb_ack_i/wb_err_i raised without wb_cyc_i/wb_stb_i", $realtime);
             end
        if ((wb_progress == 2) && !wb_stb)
           begin
           $fdisplay(fgeneral, "%t  %m WISHBONE protocol violation: wb_stb lowered without wb_err_i/wb_ack_i", $realtime);
           end
        end
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's simulation monitor ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// wishbone protocal monitor ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`module model_monitor`
44			`#(parameter TEST_NAME="unspecified",`
45			`parameter INSTANCE="none",`
46			`parameter ADD_WIDTH=32,`
47			`parameter DATA_WIDTH=32`
48			`)`
49			`(`
50			`input wire clk,`
51			`input wire reset,`
52			`input wire [ADD_WIDTH-1:0] wb_adr,`
53			`input wire wb_ack,`
54			`input wire wb_err,`
55			`input wire wb_cyc,`
56			`input wire wb_stb,`
57			`input wire wb_we,`
58			`input wire [DATA_WIDTH-1:0] wb_read,`
59			`input wire [DATA_WIDTH-1:0] wb_write,`
60			`input wire [3:0] wb_sel`
61			`);`
62			`integer fgeneral;`
63			`//`
64			`// Initialization`
65			`//`
66			`initial`
67			`begin`
68			`fgeneral = $fopen({TEST_NAME,"_",INSTANCE,"_wishbone.log"});`
69			`end`
70			`always @(posedge clk)`
71			`begin`
72			`if (wb_stb && wb_cyc && wb_ack)`
73			`begin`
74			`$fdisplay(fgeneral, "%t %m WB access %x %x %x %x %x", $realtime, wb_adr, wb_we, wb_sel, wb_read, wb_write, );`
75			`end`
76			`end`
77			`integer wb_progress;`
78			`reg [ADD_WIDTH-1:0] wb_progress_addr;`
79			`//`
80			`// WISHBONE bus checker`
81			`//`
82			`always @(posedge clk)`
83			`if (reset)`
84			`begin`
85			`wb_progress = 0;`
86			`wb_progress_addr = wb_adr;`
87			`end`
88			`else`
89			`begin`
90			`if (wb_cyc && (wb_progress != 2))`
91			`begin`
92			`wb_progress = 1;`
93			`end`
94			`if (wb_stb)`
95			`begin`
96			`if (wb_progress >= 1)`
97			`begin`
98			`if (wb_progress == 1) wb_progress_addr = wb_adr;`
99			`wb_progress = 2;`
100			`end`
101			`else`
102			`begin`
103			`$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_stb_i raised without wb_cyc_i", $realtime);`
104			`end`
105			`end`
106			`if (wb_ack & wb_err)`
107			`begin`
108			`$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_ack_i and wb_err_i raised at the same time", $realtime);`
109			`end`
110			`if ((wb_progress == 2) && (wb_progress_addr != wb_adr))`
111			`begin`
112			`$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_adr changed while waiting for wb_err_i/wb_ack_i", $realtime);`
113			`end`
114			`if (wb_ack \| wb_err)`
115			`if (wb_progress == 2)`
116			`begin`
117			`wb_progress = 0;`
118			`wb_progress_addr = wb_adr;`
119			`end`
120			`else`
121			`begin`
122			`$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_ack_i/wb_err_i raised without wb_cyc_i/wb_stb_i", $realtime);`
123			`end`
124			`if ((wb_progress == 2) && !wb_stb)`
125			`begin`
126			`$fdisplay(fgeneral, "%t %m WISHBONE protocol violation: wb_stb lowered without wb_err_i/wb_ack_i", $realtime);`
127			`end`
128			`end`
129			`endmodule`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [model_monitor.v] - Blame information for rev 131