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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  wb_slave_model                                              ////
////                                                              ////
 
module model_slave
#( parameter dwidth = 32,
   parameter awidth = 32
 )(
  input wire                  clk,
  input wire                  reset,
 
  input  wire [awidth   -1:0]  adr,
  input  wire [dwidth   -1:0]  dout,
  input  wire                  cyc,
  input  wire                  stb,
  input  wire                  we,
  input  wire [dwidth/8 -1:0]  sel,
 
  output  reg [dwidth   -1:0] din,
  output  reg                 ack,
  output  reg                 err,
  output  reg                 rty
);
 
 
 
 
 
 
 
always@(posedge clk)
  if(reset)
    begin
    din <= {dwidth{1'b0}};
    ack <= (cyc && stb);
    err <= 1'b0;
    rty <= 1'b0;
    end
 
 
 
 
 
  // Wishbone write cycle
  task wb_write;
    input [awidth -1:0] a;
    input [(dwidth/8) -1:0] s;
    input [dwidth -1:0] d;
    begin
      $display("%t %m cycle %h %h",$realtime,a,d );
      // assert wishbone signal
      adr  <= a;
      dout <= d;
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b1;
      sel  <= s;
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
    end
  endtask
  // Wishbone read cycle
  task wb_read;
    input   [awidth -1:0]  a;
    output  [dwidth -1:0]  d;
    begin
      // assert wishbone signals
      adr  <= a;
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b0;
      sel  <= {dwidth/8{1'b1}};
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      $display("%t %m  cycle %h %h",$realtime,a,din );
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
      d    <= din;
    end
  endtask
  // Wishbone compare cycle (read data from location and compare with expected data)
  task wb_cmp;
    input  [awidth-1:0] a;
    input [(dwidth/8) -1:0] s;
    input  [dwidth-1:0] d_exp;
     begin
      // assert wishbone signals
       adr  <= a;
      dout <= {dwidth{1'b0}};
      cyc  <= 1'b1;
      stb  <= 1'b1;
      we   <= 1'b0;
      sel  <= s;
      next(1);
      // wait for acknowledge from slave
      while(~ack) next(1);
      $display("%t %m   check %h %h %h",$realtime,a,din,d_exp );
      if (!(d_exp === din))  cg.fail(" Data compare error");
      // negate wishbone signals
      cyc  <= 1'b0;
      stb  <= 1'b0;
      adr  <= {awidth{1'b0}};
      dout <= {dwidth{1'b0}};
      we   <= 1'h0;
      sel  <= {dwidth/8{1'b0}};
   end
  endtask
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// wb_slave_model ////`
4			`//// ////`
5
6			`module model_slave`
7			`#( parameter dwidth = 32,`
8			`parameter awidth = 32`
9			`)(`
10			`input wire clk,`
11			`input wire reset,`
12
13			`input wire [awidth -1:0] adr,`
14			`input wire [dwidth -1:0] dout,`
15			`input wire cyc,`
16			`input wire stb,`
17			`input wire we,`
18			`input wire [dwidth/8 -1:0] sel,`
19
20			`output reg [dwidth -1:0] din,`
21			`output reg ack,`
22			`output reg err,`
23			`output reg rty`
24			`);`
25
26
27
28
29
30
31
32			`always@(posedge clk)`
33			`if(reset)`
34			`begin`
35			`din <= {dwidth{1'b0}};`
36			`ack <= (cyc && stb);`
37			`err <= 1'b0;`
38			`rty <= 1'b0;`
39			`end`
40
41
42
43
44
45			`// Wishbone write cycle`
46			`task wb_write;`
47			`input [awidth -1:0] a;`
48			`input [(dwidth/8) -1:0] s;`
49			`input [dwidth -1:0] d;`
50			`begin`
51			`$display("%t %m cycle %h %h",$realtime,a,d );`
52			`// assert wishbone signal`
53			`adr <= a;`
54			`dout <= d;`
55			`cyc <= 1'b1;`
56			`stb <= 1'b1;`
57			`we <= 1'b1;`
58			`sel <= s;`
59			`next(1);`
60			`// wait for acknowledge from slave`
61			`while(~ack) next(1);`
62			`// negate wishbone signals`
63			`cyc <= 1'b0;`
64			`stb <= 1'b0;`
65			`adr <= {awidth{1'b0}};`
66			`dout <= {dwidth{1'b0}};`
67			`we <= 1'h0;`
68			`sel <= {dwidth/8{1'b0}};`
69			`end`
70			`endtask`
71			`// Wishbone read cycle`
72			`task wb_read;`
73			`input [awidth -1:0] a;`
74			`output [dwidth -1:0] d;`
75			`begin`
76			`// assert wishbone signals`
77			`adr <= a;`
78			`dout <= {dwidth{1'b0}};`
79			`cyc <= 1'b1;`
80			`stb <= 1'b1;`
81			`we <= 1'b0;`
82			`sel <= {dwidth/8{1'b1}};`
83			`next(1);`
84			`// wait for acknowledge from slave`
85			`while(~ack) next(1);`
86			`$display("%t %m cycle %h %h",$realtime,a,din );`
87			`// negate wishbone signals`
88			`cyc <= 1'b0;`
89			`stb <= 1'b0;`
90			`adr <= {awidth{1'b0}};`
91			`dout <= {dwidth{1'b0}};`
92			`we <= 1'h0;`
93			`sel <= {dwidth/8{1'b0}};`
94			`d <= din;`
95			`end`
96			`endtask`
97			`// Wishbone compare cycle (read data from location and compare with expected data)`
98			`task wb_cmp;`
99			`input [awidth-1:0] a;`
100			`input [(dwidth/8) -1:0] s;`
101			`input [dwidth-1:0] d_exp;`
102			`begin`
103			`// assert wishbone signals`
104			`adr <= a;`
105			`dout <= {dwidth{1'b0}};`
106			`cyc <= 1'b1;`
107			`stb <= 1'b1;`
108			`we <= 1'b0;`
109			`sel <= s;`
110			`next(1);`
111			`// wait for acknowledge from slave`
112			`while(~ack) next(1);`
113			`$display("%t %m check %h %h %h",$realtime,a,din,d_exp );`
114			`if (!(d_exp === din)) cg.fail(" Data compare error");`
115			`// negate wishbone signals`
116			`cyc <= 1'b0;`
117			`stb <= 1'b0;`
118			`adr <= {awidth{1'b0}};`
119			`dout <= {dwidth{1'b0}};`
120			`we <= 1'h0;`
121			`sel <= {dwidth/8{1'b0}};`
122			`end`
123			`endtask`
124			`endmodule`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [model_slave.v] - Blame information for rev 131