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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [verilog/] [sim/] [slave] - Blame information for rev 134

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1 134 jt_eaton
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  wb_slave_model                                              ////
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////                                                              ////
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module model_slave
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#( parameter dwidth = 32,
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   parameter awidth = 32
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 )(
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  input wire                  clk,
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  input wire                  reset,
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  input  wire [awidth   -1:0]  adr,
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  input  wire [dwidth   -1:0]  dout,
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  input  wire                  cyc,
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  input  wire                  stb,
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  input  wire                  we,
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  input  wire [dwidth/8 -1:0]  sel,
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  output  reg [dwidth   -1:0] din,
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  output  reg                 ack,
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  output  reg                 err,
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  output  reg                 rty
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);
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always@(posedge clk)
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  if(reset)
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    begin
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    din <= {dwidth{1'b0}};
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    ack <= (cyc && stb);
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    err <= 1'b0;
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    rty <= 1'b0;
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    end
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  // Wishbone write cycle
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  task wb_write;
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    input [awidth -1:0] a;
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    input [(dwidth/8) -1:0] s;
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    input [dwidth -1:0] d;
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    begin
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      $display("%t %m cycle %h %h",$realtime,a,d );
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      // assert wishbone signal
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      adr  <= a;
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      dout <= d;
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      cyc  <= 1'b1;
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      stb  <= 1'b1;
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      we   <= 1'b1;
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      sel  <= s;
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      next(1);
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      // wait for acknowledge from slave
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      while(~ack) next(1);
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      // negate wishbone signals
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      cyc  <= 1'b0;
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      stb  <= 1'b0;
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      adr  <= {awidth{1'b0}};
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      dout <= {dwidth{1'b0}};
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      we   <= 1'h0;
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      sel  <= {dwidth/8{1'b0}};
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    end
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  endtask
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  // Wishbone read cycle
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  task wb_read;
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    input   [awidth -1:0]  a;
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    output  [dwidth -1:0]  d;
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    begin
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      // assert wishbone signals
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      adr  <= a;
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      dout <= {dwidth{1'b0}};
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      cyc  <= 1'b1;
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      stb  <= 1'b1;
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      we   <= 1'b0;
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      sel  <= {dwidth/8{1'b1}};
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      next(1);
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      // wait for acknowledge from slave
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      while(~ack) next(1);
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      $display("%t %m  cycle %h %h",$realtime,a,din );
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      // negate wishbone signals
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      cyc  <= 1'b0;
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      stb  <= 1'b0;
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      adr  <= {awidth{1'b0}};
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      dout <= {dwidth{1'b0}};
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      we   <= 1'h0;
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      sel  <= {dwidth/8{1'b0}};
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      d    <= din;
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    end
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  endtask
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  // Wishbone compare cycle (read data from location and compare with expected data)
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  task wb_cmp;
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    input  [awidth-1:0] a;
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    input [(dwidth/8) -1:0] s;
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    input  [dwidth-1:0] d_exp;
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     begin
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      // assert wishbone signals
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       adr  <= a;
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      dout <= {dwidth{1'b0}};
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      cyc  <= 1'b1;
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      stb  <= 1'b1;
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      we   <= 1'b0;
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      sel  <= s;
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      next(1);
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      // wait for acknowledge from slave
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      while(~ack) next(1);
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      $display("%t %m   check %h %h %h",$realtime,a,din,d_exp );
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      if (!(d_exp === din))  cg.fail(" Data compare error");
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      // negate wishbone signals
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      cyc  <= 1'b0;
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      stb  <= 1'b0;
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      adr  <= {awidth{1'b0}};
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      dout <= {dwidth{1'b0}};
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      we   <= 1'h0;
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      sel  <= {dwidth/8{1'b0}};
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   end
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  endtask
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endmodule

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