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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
model
master  default
 
 
 

 
 
wb
   
   
   
     
 
        
         adr
         
         adr
           awidth-10
         
       
 
 
        
         wdata
         
         dout
           dwidth-10
         
       
 
 
        
         rdata
         
         din
           dwidth-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
 
 
 
 
 
     
 

 

 
 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      model_master
    
  

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      model_master
    
  

 
 
 
 

 
 
 
 
 

 
 
 
 
 
 
      
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/sim/master
        verilogSourcefragment
      
 
 
      
        
        ../verilog/sim/master.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/master_copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/model_master
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
    
      fs-syn
 
 
 
 
 
 
 
 
      
        
        ../verilog/sim/master
        verilogSourcefragment
      
 
 
      
        
        ../verilog/sim/master.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/master_copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/model_master
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`model`
40			`master default`
41
42
43
44
45
46
47			`wb`
48
49
50
51
52
53
54			`adr`
55
56			`adr`
57	134	jt_eaton	`awidth-10`
58	131	jt_eaton
59
60
61
62
63			`wdata`
64
65			`dout`
66	134	jt_eaton	`dwidth-10`
67	131	jt_eaton
68
69
70
71
72			`rdata`
73
74			`din`
75	134	jt_eaton	`dwidth-10`
76	131	jt_eaton
77
78
79
80
81			`sel`
82
83			`sel`
84
85
86
87
88
89			`ack`
90
91			`ack`
92
93
94
95
96
97			`cyc`
98
99			`cyc`
100
101
102
103
104
105
106			`stb`
107
108			`stb`
109
110
111
112
113
114			`we`
115
116			`we`
117
118
119
120
121
122
123
124
125
126
127
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129
130
131
132
133
134
135	134	jt_eaton
136	131	jt_eaton
137
138
139
140	134	jt_eaton
141			`gen_verilog_sim`
142			`104.0`
143			`none`
144			`:Simulation:`
145			`./tools/verilog/gen_verilog`
146
147
148			`destination`
149			`model_master`
150
151
152
153	131	jt_eaton
154
155
156	134	jt_eaton
157			`gen_verilog_syn`
158			`104.0`
159			`none`
160			`:Synthesis:`
161			`./tools/verilog/gen_verilog`
162
163
164			`destination`
165			`model_master`
166
167
168
169	131	jt_eaton
170
171
172
173	134	jt_eaton
174	131	jt_eaton
175
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179	134	jt_eaton
180	131	jt_eaton
181
182
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185
186	134	jt_eaton
187	131	jt_eaton
188	134	jt_eaton
189			`verilog`
190
191
192			`spirit:library="Testbench"`
193			`spirit:name="toolflow"`
194			`spirit:version="verilog"/>`
195
196
197	131	jt_eaton
198	134	jt_eaton
199
200
201
202			`sim:Simulation:`
203			`Verilog`
204
205
206			`fs-sim`
207
208
209
210
211			`syn:Synthesis:`
212			`Verilog`
213
214
215			`fs-syn`
216
217
218
219
220
221
222
223
224			`doc`
225
226
227			`spirit:library="Testbench"`
228			`spirit:name="toolflow"`
229			`spirit:version="documentation"/>`
230
231			`:Documentation:`
232			`Verilog`
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
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251
252	131	jt_eaton
253			`dwidth32`
254			`awidth32`
255
256
257
258
259			`clk`
260			`wire`
261			`in`
262
263
264			`reset`
265			`wire`
266			`in`
267
268
269			`adr`
270			`reg`
271			`out`
272			`awidth-10`
273
274
275
276			`dout`
277			`reg`
278			`out`
279			`dwidth0`
280
281
282
283			`cyc`
284			`reg`
285			`out`
286
287
288			`stb`
289			`reg`
290			`out`
291
292
293			`we`
294			`reg`
295			`out`
296
297
298
299			`sel`
300			`reg`
301			`out`
302			`dwidth/8-10`
303
304
305
306			`din`
307			`wire`
308			`in`
309			`dwidth-10`
310
311
312
313			`ack`
314			`wire`
315			`in`
316
317
318			`err`
319			`wire`
320			`in`
321
322
323			`rty`
324			`wire`
325			`in`
326
327
328
329
330
331
332
333
334
335
336
337	134	jt_eaton
338	131	jt_eaton
339
340	134	jt_eaton
341			`fs-sim`
342	131	jt_eaton
343	134	jt_eaton
344
345			`../verilog/sim/master`
346			`verilogSourcefragment`
347
348
349
350
351
352			`../verilog/sim/master.tasks`
353			`verilogSourcefragment`
354
355
356
357
358
359			`../verilog/master_copyright`
360			`verilogSourceinclude`
361
362
363
364
365
366			`../verilog/sim/model_master`
367			`verilogSourcemodule`
368
369
370
371
372			`dest_dir../views/sim/`
373			`verilogSourcelibraryDir`
374
375
376
377
378
379
380
381			`fs-syn`
382
383
384
385
386
387
388
389
390
391
392			`../verilog/sim/master`
393			`verilogSourcefragment`
394
395
396
397
398
399			`../verilog/sim/master.tasks`
400			`verilogSourcefragment`
401
402
403
404
405
406			`../verilog/master_copyright`
407			`verilogSourceinclude`
408
409
410
411
412
413			`../verilog/sim/model_master`
414			`verilogSourcemodule`
415
416
417
418
419			`dest_dir../views/sim/`
420			`verilogSourcelibraryDir`
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437	131	jt_eaton