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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_monitor.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
model
monitor
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
                
                        
                                verilog
                                verilog
                                model_monitor
                                
                                        
                                                ADD_WIDTH
                                                8
                                        
                                        
                                                DATAWIDTH
                                                32
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
       
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
       
 
 
 

TEST_NAME"unspecified"
INSTANCE"none"
ADD_WIDTH32
DATA_WIDTH32

 

 
clk
wire
in

 
reset
wire
in

 
wb_adr
wire
in
ADD_WIDTH-10

 
wb_ack
wire
in

 
wb_err
wire
in

 
wb_cyc
wire
in

 
wb_stb
wire
in

 
wb_we
wire
in

 
 
wb_read
wire
in
DATA_WIDTH-10

 
wb_write
wire
in
DATA_WIDTH-10

 
 
wb_sel
wire
in
30

 

 

 
  
 
 
    
      fs-sim
 
      
        dest_dir../verilog/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
 
      
        dest_dir../verilog/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`model`
40			`monitor`
41	131	jt_eaton
42
43
44
45
46
47
48
49
50
51
52
53	135	jt_eaton
54	131	jt_eaton
55
56
57
58
59	135	jt_eaton
60
61			`verilog`
62			`verilog`
63			`model_monitor`
64
65
66			`ADD_WIDTH`
67			`8`
68
69
70			`DATAWIDTH`
71			`32`
72
73
74
75			`fs-sim`
76
77
78
79	131	jt_eaton
80	135	jt_eaton
81
82	131	jt_eaton
83
84	135	jt_eaton
85			`rtl`
86			`verilog:Kactus2:`
87			`verilog`
88
89
90
91	131	jt_eaton
92	135	jt_eaton
93	131	jt_eaton
94	135	jt_eaton
95			`TEST_NAME"unspecified"`
96			`INSTANCE"none"`
97			`ADD_WIDTH32`
98			`DATA_WIDTH32`
99
100	131	jt_eaton
101	135	jt_eaton
102	131	jt_eaton
103	135	jt_eaton	`clk`
104			`wire`
105			`in`
106
107	131	jt_eaton
108	135	jt_eaton	`reset`
109			`wire`
110			`in`
111
112	131	jt_eaton
113	135	jt_eaton	`wb_adr`
114			`wire`
115			`in`
116			`ADD_WIDTH-10`
117
118	131	jt_eaton
119	135	jt_eaton	`wb_ack`
120			`wire`
121			`in`
122
123	131	jt_eaton
124	135	jt_eaton	`wb_err`
125			`wire`
126			`in`
127
128	131	jt_eaton
129	135	jt_eaton	`wb_cyc`
130			`wire`
131			`in`
132
133	131	jt_eaton
134	135	jt_eaton	`wb_stb`
135			`wire`
136			`in`
137
138	131	jt_eaton
139	135	jt_eaton	`wb_we`
140			`wire`
141			`in`
142
143	131	jt_eaton
144
145	135	jt_eaton	`wb_read`
146			`wire`
147			`in`
148			`DATA_WIDTH-10`
149
150	131	jt_eaton
151	135	jt_eaton	`wb_write`
152			`wire`
153			`in`
154			`DATA_WIDTH-10`
155
156	131	jt_eaton
157
158	135	jt_eaton	`wb_sel`
159			`wire`
160			`in`
161			`30`
162
163	131	jt_eaton
164	135	jt_eaton
165	131	jt_eaton
166	135	jt_eaton
167	131	jt_eaton
168	135	jt_eaton
169	131	jt_eaton
170
171	135	jt_eaton
172			`fs-sim`
173	131	jt_eaton
174	135	jt_eaton
175			`dest_dir../verilog/sim/`
176			`verilogSourcelibraryDir`
177
178	131	jt_eaton
179
180
181
182	135	jt_eaton
183	131	jt_eaton
184
185	135	jt_eaton
186			`fs-syn`
187	131	jt_eaton
188
189	135	jt_eaton
190			`dest_dir../verilog/syn/`
191			`verilogSourcelibraryDir`
192
193	131	jt_eaton
194
195	135	jt_eaton
196	131	jt_eaton
197
198
199	135	jt_eaton
200	131	jt_eaton
201
202
203
204
205	135	jt_eaton
206
207
208
209
210
211
212

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_monitor.xml] - Blame information for rev 135