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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_slave.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
model
slave
 
 
 

 
 
wb
   
 
 
  
      
        
     
 
        
         adr
         
         adr
           wb_addr_width-10
         
       
 
 
        
         wdata
         
         dout
           wb_data_width-10
         
       
 
 
        
         rdata
         
         din
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
     
 
 
        
      
   
 
 

 

 
 
 
 
 
 
 
 
 

 
 
 
                
                        
                                verilog
                                verilog
                                cde_sram_def
                                
                                        
                                                awidth
                                                32
                                        
                                        
                                                awidth
                                                32
                                        
                                
                                
fs-sim
                                
                        
                
 
 
       
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
       
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        dest_dir../verilog/sim/
        verilogSourcelibraryDir
      
 
    
 
    
      fs-syn
 
 
      
        dest_dir../verilog/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`model`
40			`slave`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton	`wb`
48
49	131	jt_eaton
50
51	135	jt_eaton
52
53
54
55	131	jt_eaton
56	135	jt_eaton
57			`adr`
58
59			`adr`
60			`wb_addr_width-10`
61
62
63	131	jt_eaton
64
65	135	jt_eaton
66			`wdata`
67
68			`dout`
69			`wb_data_width-10`
70
71
72	131	jt_eaton
73
74	135	jt_eaton
75			`rdata`
76
77			`din`
78			`wb_data_width-10`
79
80
81	131	jt_eaton
82
83	135	jt_eaton
84			`sel`
85
86			`sel`
87
88
89	131	jt_eaton
90
91	135	jt_eaton
92			`ack`
93
94			`ack`
95
96
97	131	jt_eaton
98
99	135	jt_eaton
100			`cyc`
101
102			`cyc`
103
104
105	131	jt_eaton
106
107
108	135	jt_eaton
109			`stb`
110
111			`stb`
112
113
114	131	jt_eaton
115
116	135	jt_eaton
117			`we`
118
119			`we`
120
121
122	131	jt_eaton
123
124	135	jt_eaton
125	131	jt_eaton
126	135	jt_eaton
127
128
129
130	131	jt_eaton
131
132	135	jt_eaton
133	131	jt_eaton
134	135	jt_eaton
135	131	jt_eaton
136
137
138
139
140
141
142
143
144	135	jt_eaton
145	131	jt_eaton
146
147
148	135	jt_eaton
149
150			`verilog`
151			`verilog`
152			`cde_sram_def`
153
154
155			`awidth`
156			`32`
157
158
159			`awidth`
160			`32`
161
162
163
164			`fs-sim`
165
166
167
168	131	jt_eaton
169	135	jt_eaton
170
171	131	jt_eaton
172
173	135	jt_eaton
174			`rtl`
175			`verilog:Kactus2:`
176			`verilog`
177
178
179
180	131	jt_eaton
181	135	jt_eaton
182	131	jt_eaton
183	135	jt_eaton
184			`dwidth32`
185			`awidth32`
186
187	131	jt_eaton
188	135	jt_eaton
189	131	jt_eaton
190	135	jt_eaton	`clk`
191			`wire`
192			`in`
193
194	131	jt_eaton
195	135	jt_eaton	`reset`
196			`wire`
197			`in`
198
199	131	jt_eaton
200	135	jt_eaton	`adr`
201			`reg`
202			`out`
203			`awidth-10`
204
205	131	jt_eaton
206
207	135	jt_eaton	`dout`
208			`reg`
209			`out`
210			`dwidth0`
211
212	131	jt_eaton
213
214	135	jt_eaton	`cyc`
215			`reg`
216			`out`
217
218	131	jt_eaton
219	135	jt_eaton	`stb`
220			`reg`
221			`out`
222
223	131	jt_eaton
224	135	jt_eaton	`we`
225			`reg`
226			`out`
227
228	131	jt_eaton
229
230	135	jt_eaton	`sel`
231			`reg`
232			`out`
233			`dwidth/8-10`
234
235	131	jt_eaton
236
237	135	jt_eaton	`din`
238			`wire`
239			`in`
240			`dwidth-10`
241
242	131	jt_eaton
243
244	135	jt_eaton	`ack`
245			`wire`
246			`in`
247
248	131	jt_eaton
249	135	jt_eaton	`err`
250			`wire`
251			`in`
252
253	131	jt_eaton
254	135	jt_eaton	`rty`
255			`wire`
256			`in`
257
258	131	jt_eaton
259
260	135	jt_eaton
261	131	jt_eaton
262	135	jt_eaton
263	131	jt_eaton
264
265
266
267
268
269
270	135	jt_eaton
271	131	jt_eaton
272
273	135	jt_eaton
274			`fs-sim`
275	131	jt_eaton
276	135	jt_eaton
277			`dest_dir../verilog/sim/`
278			`verilogSourcelibraryDir`
279
280	131	jt_eaton
281	135	jt_eaton
282	131	jt_eaton
283	135	jt_eaton
284			`fs-syn`
285	131	jt_eaton
286
287	135	jt_eaton
288			`dest_dir../verilog/syn/`
289			`verilogSourcelibraryDir`
290
291	131	jt_eaton
292
293	135	jt_eaton
294	131	jt_eaton
295
296	135	jt_eaton
297	131	jt_eaton
298
299	135	jt_eaton
300
301
302

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_slave.xml] - Blame information for rev 135