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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
wishbone
wb_memory
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
 
 
 
 

 
wb_memory/sim
 

 
 
 
   default
   def
   def_tb
   def_lint
   
   wb_addr_width24
   wb_data_width32
   wb_byte_lanes4
   dat_width32
   adr_width14
   mem_size16384
   
 
 
 
 
 
 
 

 
 
 
 
 
 

 
 
 

wb_memory_def_tb
def_tb

    PERIOD40
    TIMEOUT100000


  
  wb_memory_defTB.test.dut
  


  icaruscoverage


 
 

wb_memory_def_lint
def_lint

  rtl_check


 
 

 
 
 
 
 
 

 

default
wb_memory_def_lint


 
 
 
 
 
 

 

default
wb_memory_def_tb
  
  
 


 
 

 
 

 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`wishbone`
12			`wb_memory`
13
14			`2`
15			`_`
16			`_`
17			`_`
18			`VARIANT`
19
20	135	jt_eaton
21
22			`TestBenches`
23			`sim`
24			`testbenches`
25			`testbench`
26			`version`
27
28
29			`Fpgas`
30			`syn`
31			`ise`
32			`chip`
33			`variant`
34
35
36	131	jt_eaton
37	135	jt_eaton
38
39	131	jt_eaton
40
41			`/doc`
42
43
44
45
46
47
48
49
50
51			`wb_memory/sim`
52
53	134	jt_eaton
54	131	jt_eaton
55
56	134	jt_eaton
57			`default`
58			`def`
59			`def_tb`
60			`def_lint`
61
62			`wb_addr_width24`
63			`wb_data_width32`
64			`wb_byte_lanes4`
65			`dat_width32`
66			`adr_width14`
67			`mem_size16384`
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83	131	jt_eaton
84
85
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88			`wb_memory_def_tb`
89			`def_tb`
90
91			`PERIOD40`
92			`TIMEOUT100000`
93
94
95
96			`wb_memory_defTB.test.dut`
97
98
99
100			`icaruscoverage`
101
102
103
104
105
106			`wb_memory_def_lint`
107			`def_lint`
108
109			`rtl_check`
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124			`default`
125			`wb_memory_def_lint`
126
127
128
129
130
131
132
133
134
135
136
137			`default`
138			`wb_memory_def_tb`
139	134	jt_eaton
140
141
142	131	jt_eaton
143
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [componentCfg.xml] - Blame information for rev 135