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reg waitst;
 
 
   always @ (posedge clk_i or posedge rst_i)
     if (rst_i)                  waitst <= 1'b0;
     else
     if (!ack_o)
       begin
        if (cyc_i & stb_i)       waitst <= 1'b1;
        else                     waitst <= waitst;
       end
     else                        waitst <= 1'b0;
 
 
 
 
   // ack_o
   always @ (posedge clk_i or posedge rst_i)
     if (rst_i)                             ack_o <= 1'b0;
     else
     if (!ack_o)
       begin
        if (cyc_i & stb_i & waitst )        ack_o <= 1'b1;
        else                                ack_o <= ack_o;
       end
     else                                   ack_o <= 1'b0;
 
 
 
 
assign sram_wr        =   we_i & ack_o;
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3
4			`reg waitst;`
5
6
7			`always @ (posedge clk_i or posedge rst_i)`
8			`if (rst_i) waitst <= 1'b0;`
9			`else`
10			`if (!ack_o)`
11			`begin`
12			`if (cyc_i & stb_i) waitst <= 1'b1;`
13			`else waitst <= waitst;`
14			`end`
15			`else waitst <= 1'b0;`
16
17
18
19
20			`// ack_o`
21			`always @ (posedge clk_i or posedge rst_i)`
22			`if (rst_i) ack_o <= 1'b0;`
23			`else`
24			`if (!ack_o)`
25			`begin`
26			`if (cyc_i & stb_i & waitst ) ack_o <= 1'b1;`
27			`else ack_o <= ack_o;`
28			`end`
29			`else ack_o <= 1'b0;`
30
31
32
33
34			`assign sram_wr = we_i & ack_o;`
35
36
37
38

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [verilog/] [top.body] - Blame information for rev 131