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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_memory
def  default
 
 
 

 
 
 slave_clk
  
  
  
    
      
        clk
        clk_i
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        rst_i
      
    
 
 
 
wb
   
   
     
     
 
        
         adr
         
         adr_i
           wb_addr_width-10
         
       
 
 
 
        
         wdata
         
         dat_i
           wb_data_width-10
         
       
 
 
        
         rdata
         
         dat_o
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel_i
           wb_byte_lanes-10
         
       
 
 
        
         we
         
         we_i
         
       
 
 
        
         cyc
         
         cyc_i
         
       
 
 
        
         stb
         
         stb_i
         
       
 
 
        
         ack
         
         ack_o
         reg
         
       
 
 
     
 

 

 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 
 
 

       
 
 
 
              
              Hierarchical
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

   wb_addr_width24
   wb_data_width32
   wb_byte_lanes4
   dat_width32
   adr_width12
   mem_size16384
   SRAM_MEM_0_FILE"NONE"
   SRAM_MEM_1_FILE"NONE"
   SRAM_MEM_2_FILE"NONE"
   SRAM_MEM_3_FILE"NONE"
 

 
 
 

 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def default`
41
42
43
44
45
46
47			`slave_clk`
48
49
50
51
52
53			`clk`
54			`clk_i`
55
56
57
58
59
60			`slave_reset`
61
62
63
64
65
66			`reset`
67			`rst_i`
68
69
70
71
72
73			`wb`
74
75
76
77
78
79
80			`adr`
81
82			`adr_i`
83			`wb_addr_width-10`
84
85
86
87
88
89
90			`wdata`
91
92			`dat_i`
93			`wb_data_width-10`
94
95
96
97
98
99			`rdata`
100
101			`dat_o`
102			`wb_data_width-10`
103
104
105
106
107
108			`sel`
109
110			`sel_i`
111			`wb_byte_lanes-10`
112
113
114
115
116
117			`we`
118
119			`we_i`
120
121
122
123
124
125			`cyc`
126
127			`cyc_i`
128
129
130
131
132
133			`stb`
134
135			`stb_i`
136
137
138
139
140
141			`ack`
142
143			`ack_o`
144			`reg`
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162	133	jt_eaton
163	131	jt_eaton
164	133	jt_eaton	`elab_verilog`
165			`102.1`
166			`none`
167			`:Simulation:`
168			`./tools/verilog/elab_verilog`
169
170
171			`dest_dir`
172			`io_ports`
173
174
175
176
177
178
179
180
181	131	jt_eaton	`gen_verilog`
182			`104.0`
183			`none`
184			`common`
185			`./tools/verilog/gen_verilog`
186
187
188			`destination`
189			`top`
190
191
192			`dest_dir`
193			`../verilog`
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210			`fs-common`
211
212
213
214
215			`../verilog/top.body`
216			`verilogSourcefragment`
217
218
219
220
221
222
223
224			`fs-sim`
225
226
227
228			`../verilog/copyright.v`
229			`verilogSourceinclude`
230
231
232
233
234			`../verilog/common/top`
235			`verilogSourcemodule`
236
237
238
239
240
241
242
243
244
245			`fs-syn`
246
247
248
249			`../verilog/copyright.v`
250			`verilogSourceinclude`
251
252
253
254
255			`../verilog/common/top`
256			`verilogSourcemodule`
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278			`Hierarchical`
279
280
281			`spirit:library="wishbone"`
282			`spirit:name="wb_memory"`
283			`spirit:version="def.design"/>`
284
285
286
287			`verilog`
288
289
290			`spirit:library="Testbench"`
291			`spirit:name="toolflow"`
292			`spirit:version="verilog"/>`
293
294
295
296
297
298
299
300
301
302			`commoncommon`
303
304			`Verilog`
305
306
307			`fs-common`
308
309
310
311
312
313			`sim:Simulation:`
314
315			`Verilog`
316
317
318			`fs-sim`
319
320
321
322
323			`syn:Synthesis:`
324
325			`Verilog`
326
327
328			`fs-syn`
329
330
331
332
333
334
335			`doc`
336
337
338			`spirit:library="Testbench"`
339			`spirit:name="toolflow"`
340			`spirit:version="documentation"/>`
341
342			`:Documentation:`
343			`Verilog`
344
345
346
347
348
349
350
351
352			`wb_addr_width24`
353			`wb_data_width32`
354			`wb_byte_lanes4`
355			`dat_width32`
356			`adr_width12`
357			`mem_size16384`
358			`SRAM_MEM_0_FILE"NONE"`
359			`SRAM_MEM_1_FILE"NONE"`
360			`SRAM_MEM_2_FILE"NONE"`
361			`SRAM_MEM_3_FILE"NONE"`
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377