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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_memory
def  default
 
 
 

 
 
 slave_clk
  
  
  
    
      
        clk
        clk_i
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        rst_i
      
    
 
 
 
wb
   
   
     
     
 
        
         adr
         
         adr_i
           wb_addr_width-10
         
       
 
 
 
        
         wdata
         
         dat_i
           wb_data_width-10
         
       
 
 
        
         rdata
         
         dat_o
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel_i
           wb_byte_lanes-10
         
       
 
 
        
         we
         
         we_i
         
       
 
 
        
         cyc
         
         cyc_i
         
       
 
 
        
         stb
         
         stb_i
         
       
 
 
        
         ack
         
         ack_o
         reg
         
       
 
 
     
 

 

 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      wb_memory_def
    
  

 
 
 
 
 

 
 
 
 
 
 
 
 

       
 
 
 
              
              Hierarchical
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

   wb_addr_width24
   wb_data_width32
   wb_byte_lanes4
   dat_width32
   adr_width14
   mem_size16384
   SRAM_MEM_0_FILE"NONE"
   SRAM_MEM_1_FILE"NONE"
   SRAM_MEM_2_FILE"NONE"
   SRAM_MEM_3_FILE"NONE"
 

 
 
 

 
 
 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_memory_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_memory_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def default`
41
42
43
44
45
46
47			`slave_clk`
48
49
50
51
52
53			`clk`
54			`clk_i`
55
56
57
58
59
60			`slave_reset`
61
62
63
64
65
66			`reset`
67			`rst_i`
68
69
70
71
72
73			`wb`
74
75
76
77
78
79
80			`adr`
81
82			`adr_i`
83			`wb_addr_width-10`
84
85
86
87
88
89
90			`wdata`
91
92			`dat_i`
93			`wb_data_width-10`
94
95
96
97
98
99			`rdata`
100
101			`dat_o`
102			`wb_data_width-10`
103
104
105
106
107
108			`sel`
109
110			`sel_i`
111			`wb_byte_lanes-10`
112
113
114
115
116
117			`we`
118
119			`we_i`
120
121
122
123
124
125			`cyc`
126
127			`cyc_i`
128
129
130
131
132
133			`stb`
134
135			`stb_i`
136
137
138
139
140
141			`ack`
142
143			`ack_o`
144			`reg`
145
146
147
148
149
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151
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153
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155
156
157
158
159
160
161
162	133	jt_eaton
163
164
165
166	131	jt_eaton	`gen_verilog`
167			`104.0`
168			`none`
169			`common`
170			`./tools/verilog/gen_verilog`
171
172
173			`destination`
174	134	jt_eaton	`wb_memory_def`
175	131	jt_eaton
176
177
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180
181
182
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185
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187
188
189
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195
196
197
198			`Hierarchical`
199
200
201			`spirit:library="wishbone"`
202			`spirit:name="wb_memory"`
203			`spirit:version="def.design"/>`
204
205
206
207			`verilog`
208
209
210			`spirit:library="Testbench"`
211			`spirit:name="toolflow"`
212			`spirit:version="verilog"/>`
213
214
215
216
217
218
219
220
221
222			`commoncommon`
223
224			`Verilog`
225
226
227			`fs-common`
228
229
230
231
232
233			`sim:Simulation:`
234
235			`Verilog`
236
237
238			`fs-sim`
239
240
241
242
243			`syn:Synthesis:`
244
245			`Verilog`
246
247
248			`fs-syn`
249
250
251
252
253
254
255			`doc`
256
257
258			`spirit:library="Testbench"`
259			`spirit:name="toolflow"`
260			`spirit:version="documentation"/>`
261
262			`:Documentation:`
263			`Verilog`
264
265
266
267
268
269
270
271
272			`wb_addr_width24`
273			`wb_data_width32`
274			`wb_byte_lanes4`
275			`dat_width32`
276	134	jt_eaton	`adr_width14`
277	131	jt_eaton	`mem_size16384`
278			`SRAM_MEM_0_FILE"NONE"`
279			`SRAM_MEM_1_FILE"NONE"`
280			`SRAM_MEM_2_FILE"NONE"`
281			`SRAM_MEM_3_FILE"NONE"`
282
283
284
285
286
287
288
289
290
291
292
293	134	jt_eaton
294	131	jt_eaton
295
296	134	jt_eaton
297			`fs-common`
298	131	jt_eaton
299
300	134	jt_eaton
301
302			`../verilog/top.body`
303			`verilogSourcefragment`
304
305
306
307
308
309
310
311			`fs-sim`
312
313
314
315			`../verilog/copyright`
316			`verilogSourceinclude`
317
318
319
320
321			`../verilog/common/wb_memory_def`
322			`verilogSourcemodule`
323
324
325
326
327			`dest_dir`
328			`../views/sim/`
329			`verilogSourcelibraryDir`
330
331
332
333
334
335
336
337
338
339
340
341
342
343			`fs-syn`
344
345
346
347			`../verilog/copyright`
348			`verilogSourceinclude`
349
350
351
352
353			`../verilog/common/wb_memory_def`
354			`verilogSourcemodule`
355
356
357
358
359			`dest_dir`
360			`../views/syn/`
361			`verilogSourcelibraryDir`
362
363
364
365
366
367
368
369
370
371
372
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378	131	jt_eaton