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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_memory
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      wb_memory_def_tb
    
  

 
 
 

 
 
 
 

 
 
       
 
 
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/common/wb_memory_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
    
      fs-lint
 
 
      
        
        ../verilog/common/wb_memory_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60	134	jt_eaton	`wb_memory_def_tb`
61	131	jt_eaton
62
63
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65
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67
68
69
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71
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79
80			`Params`
81
82
83			`spirit:library="wishbone"`
84			`spirit:name="wb_memory"`
85			`spirit:version="def_dut.params"/>`
86
87
88
89
90			`Bfm`
91
92			`spirit:library="wishbone"`
93			`spirit:name="wb_memory"`
94			`spirit:version="bfm.design"/>`
95
96
97
98
99
100			`icarus`
101
102
103			`spirit:library="Testbench"`
104			`spirit:name="toolflow"`
105			`spirit:version="icarus"/>`
106
107
108
109
110
111
112
113			`commoncommon`
114			`Verilog`
115
116
117			`fs-common`
118
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121
122
123			`sim:Simulation:`
124			`Verilog`
125
126
127			`fs-sim`
128
129
130
131
132			`lint:Lint:`
133			`Verilog`
134
135
136			`fs-lint`
137
138
139
140
141
142
143
144
145
146
147
148
149
150
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153
154			`fs-common`
155
156
157
158
159			`../verilog/tb.ext`
160			`verilogSourcefragment`
161
162
163
164
165
166
167			`fs-sim`
168
169
170
171
172	134	jt_eaton	`../verilog/common/wb_memory_def_tb`
173	131	jt_eaton	`verilogSourcemodule`
174
175
176
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178
179
180
181
182
183
184			`fs-lint`
185
186
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189	134	jt_eaton	`../verilog/common/wb_memory_def_tb`
190	131	jt_eaton	`verilogSourcemodule`
191
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 134