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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
wishbone
wb_uart16550
 
 
2
_
_
_
VARIANT
 
 

 
/doc
 

 
 
 
 
 
 
    
 
          
            default
            
            PRESCALER_PRESET16'h1234
           
          
 
    
 
 

 
wb_uart16550/sim
 
 
 
 
 

 
 

wb_uart16550_def_tb
def_tb

    PERIOD40
    TIMEOUT100000

 
root.dutwb
 

  
  wb_uart16550_def
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus16_lit_tb
bus16_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_lit
  TB.test.dut
  


  icaruscoverage

 

 
 
 

wb_uart16550_bus16_big_tb
bus16_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus32_lit_tb
bus32_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_lit
  TB.test.dut
  


  icaruscoverage


 
 

wb_uart16550_bus32_big_tb
bus32_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 
 
 

wb_uart16550_def_lint
def_lint

  rtl_check


 
 
 
 

wb_uart16550_bus16_lit_lint
bus16_lit_lint

  rtl_check

 

 
 
 

wb_uart16550_bus16_big_lint
bus16_big_lint

  rtl_check


 
 
 
 

wb_uart16550_bus32_lit_lint
bus32_lit_lint

  rtl_check


 
 

wb_uart16550_bus32_big_lint
bus32_big_lint

  rtl_check


 
 
 

 
 
 
 
 
 
 

 

default
wb_uart16550_def_lint
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_lint
default

 
 

bus16_big_default
wb_uart16550_bus16_big_lint
default

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_lint
default

 
 
 

bus32_big_default
wb_uart16550_bus32_big_lint
default

 
 
 

 
 
 
 
 
 
 
 

 

default
wb_uart16550_def_tb
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_tb
default

 
 

bus16_big_default
wb_uart16550_bus16_big_tb
default

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_tb
default

 
 
 

bus32_big_default
wb_uart16550_bus32_big_tb
default

 
 
 

 
 
 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`wishbone`
12			`wb_uart16550`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21
22
23
24			`/doc`
25
26
27
28
29
30
31
32
33
34
35
36			`default`
37
38			`PRESCALER_PRESET16'h1234`
39
40
41
42
43
44
45
46
47			`wb_uart16550/sim`
48
49
50
51
52
53
54
55
56
57			`wb_uart16550_def_tb`
58			`def_tb`
59
60			`PERIOD40`
61			`TIMEOUT100000`
62
63
64			`root.dutwb`
65
66
67
68			`wb_uart16550_def`
69			`TB.test.dut`
70
71
72
73			`icaruscoverage`
74
75
76
77
78
79
80
81
82			`wb_uart16550_bus16_lit_tb`
83			`bus16_lit_tb`
84
85			`PERIOD40`
86			`TIMEOUT100000`
87
88			`root.dutwb`
89
90
91			`wb_uart16550_bus16_lit`
92			`TB.test.dut`
93
94
95
96			`icaruscoverage`
97
98
99
100
101
102
103
104			`wb_uart16550_bus16_big_tb`
105			`bus16_big_tb`
106
107			`PERIOD40`
108			`TIMEOUT100000`
109
110			`root.dutwb`
111
112
113			`wb_uart16550_bus16_big`
114			`TB.test.dut`
115
116
117
118			`icaruscoverage`
119
120
121
122
123
124
125
126
127			`wb_uart16550_bus32_lit_tb`
128			`bus32_lit_tb`
129
130			`PERIOD40`
131			`TIMEOUT100000`
132
133			`root.dutwb`
134
135
136			`wb_uart16550_bus32_lit`
137			`TB.test.dut`
138
139
140
141			`icaruscoverage`
142
143
144
145
146
147			`wb_uart16550_bus32_big_tb`
148			`bus32_big_tb`
149
150			`PERIOD40`
151			`TIMEOUT100000`
152
153			`root.dutwb`
154
155
156			`wb_uart16550_bus32_big`
157			`TB.test.dut`
158
159
160
161			`icaruscoverage`
162
163
164
165
166
167
168
169
170
171
172			`wb_uart16550_def_lint`
173			`def_lint`
174
175			`rtl_check`
176
177
178
179
180
181
182
183			`wb_uart16550_bus16_lit_lint`
184			`bus16_lit_lint`
185
186			`rtl_check`
187
188
189
190
191
192
193
194			`wb_uart16550_bus16_big_lint`
195			`bus16_big_lint`
196
197			`rtl_check`
198
199
200
201
202
203
204
205			`wb_uart16550_bus32_lit_lint`
206			`bus32_lit_lint`
207
208			`rtl_check`
209
210
211
212
213
214			`wb_uart16550_bus32_big_lint`
215			`bus32_big_lint`
216
217			`rtl_check`
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234			`default`
235			`wb_uart16550_def_lint`
236			`default`
237
238
239
240
241
242
243			`bus16_lit_default`
244			`wb_uart16550_bus16_lit_lint`
245			`default`
246
247
248
249
250			`bus16_big_default`
251			`wb_uart16550_bus16_big_lint`
252			`default`
253
254
255
256
257
258
259			`bus32_lit_default`
260			`wb_uart16550_bus32_lit_lint`
261			`default`
262
263
264
265
266
267			`bus32_big_default`
268			`wb_uart16550_bus32_big_lint`
269			`default`
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286			`default`
287			`wb_uart16550_def_tb`
288			`default`
289
290
291
292
293
294
295			`bus16_lit_default`
296			`wb_uart16550_bus16_lit_tb`
297			`default`
298
299
300
301
302			`bus16_big_default`
303			`wb_uart16550_bus16_big_tb`
304			`default`
305
306
307
308
309
310
311			`bus32_lit_default`
312			`wb_uart16550_bus32_lit_tb`
313			`default`
314
315
316
317
318
319			`bus32_big_default`
320			`wb_uart16550_bus32_big_tb`
321			`default`
322
323
324
325
326
327
328
329
330
331
332
333
334