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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
wishbone
wb_uart16550
 
 
2
_
_
_
VARIANT
 
 

 
/doc
 

 
 
 
 
 
 
    
 
          
            default
            def
            def_tb
            def_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH8
           
          
 
          
            bus16
            bus16_lit
            bus16_lit_tb
            bus16_lit_lint
            bus16_big
            bus16_big_tb
            bus16_big_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH16
            WB_BYTE_LANES2
           
          
 
          
            bus32
            bus32_lit
            bus32_lit_tb
            bus32_lit_lint
            bus32_big
            bus32_big_tb
            bus32_big_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH32
            WB_BYTE_LANES4
           
          
    
 
 

 
wb_uart16550/sim
 
 
 
 
 

 
 

wb_uart16550_def_tb
def_tb

    PERIOD40
    TIMEOUT100000

 
root.dutwb
 

  
  wb_uart16550_def
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus16_lit_tb
bus16_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_lit
  TB.test.dut
  


  icaruscoverage

 

 
 
 

wb_uart16550_bus16_big_tb
bus16_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus32_lit_tb
bus32_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_lit
  TB.test.dut
  


  icaruscoverage


 
 

wb_uart16550_bus32_big_tb
bus32_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 
 
 

wb_uart16550_def_lint
def_lint

  rtl_check


 
 
 
 

wb_uart16550_bus16_lit_lint
bus16_lit_lint

  rtl_check

 

 
 
 

wb_uart16550_bus16_big_lint
bus16_big_lint

  rtl_check


 
 
 
 

wb_uart16550_bus32_lit_lint
bus32_lit_lint

  rtl_check


 
 

wb_uart16550_bus32_big_lint
bus32_big_lint

  rtl_check


 
 
 

 
 
 
 
 
 
 

 

default
wb_uart16550_def_lint
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_lint
default

 
 

bus16_big_default
wb_uart16550_bus16_big_lint
default

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_lint
default

 
 
 

bus32_big_default
wb_uart16550_bus32_big_lint
default

 
 
 

 
 
 
 
 
 
 
 

 

default
wb_uart16550_def_tb
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_tb
bus16

 
 

bus16_big_default
wb_uart16550_bus16_big_tb
bus16

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_tb
bus32

 
 
 

bus32_big_default
wb_uart16550_bus32_big_tb
bus32

 
 
 

 
 
 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`wishbone`
12			`wb_uart16550`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21
22
23
24			`/doc`
25
26
27
28
29
30
31
32
33
34
35
36			`default`
37	134	jt_eaton	`def`
38			`def_tb`
39			`def_lint`
40	131	jt_eaton
41			`PRESCALER_PRESET16'h1234`
42	134	jt_eaton	`WB_ADDR_WIDTH8`
43			`WB_DATA_WIDTH8`
44	131	jt_eaton
45
46
47	134	jt_eaton
48			`bus16`
49			`bus16_lit`
50			`bus16_lit_tb`
51			`bus16_lit_lint`
52			`bus16_big`
53			`bus16_big_tb`
54			`bus16_big_lint`
55
56			`PRESCALER_PRESET16'h1234`
57			`WB_ADDR_WIDTH8`
58			`WB_DATA_WIDTH16`
59			`WB_BYTE_LANES2`
60
61
62
63
64			`bus32`
65			`bus32_lit`
66			`bus32_lit_tb`
67			`bus32_lit_lint`
68			`bus32_big`
69			`bus32_big_tb`
70			`bus32_big_lint`
71
72			`PRESCALER_PRESET16'h1234`
73			`WB_ADDR_WIDTH8`
74			`WB_DATA_WIDTH32`
75			`WB_BYTE_LANES4`
76
77
78	131	jt_eaton
79
80
81
82
83			`wb_uart16550/sim`
84
85
86
87
88
89
90
91
92
93			`wb_uart16550_def_tb`
94			`def_tb`
95
96			`PERIOD40`
97			`TIMEOUT100000`
98
99
100			`root.dutwb`
101
102
103
104			`wb_uart16550_def`
105			`TB.test.dut`
106
107
108
109			`icaruscoverage`
110
111
112
113
114
115
116
117
118			`wb_uart16550_bus16_lit_tb`
119			`bus16_lit_tb`
120
121			`PERIOD40`
122			`TIMEOUT100000`
123
124			`root.dutwb`
125
126
127			`wb_uart16550_bus16_lit`
128			`TB.test.dut`
129
130
131
132			`icaruscoverage`
133
134
135
136
137
138
139
140			`wb_uart16550_bus16_big_tb`
141			`bus16_big_tb`
142
143			`PERIOD40`
144			`TIMEOUT100000`
145
146			`root.dutwb`
147
148
149			`wb_uart16550_bus16_big`
150			`TB.test.dut`
151
152
153
154			`icaruscoverage`
155
156
157
158
159
160
161
162
163			`wb_uart16550_bus32_lit_tb`
164			`bus32_lit_tb`
165
166			`PERIOD40`
167			`TIMEOUT100000`
168
169			`root.dutwb`
170
171
172			`wb_uart16550_bus32_lit`
173			`TB.test.dut`
174
175
176
177			`icaruscoverage`
178
179
180
181
182
183			`wb_uart16550_bus32_big_tb`
184			`bus32_big_tb`
185
186			`PERIOD40`
187			`TIMEOUT100000`
188
189			`root.dutwb`
190
191
192			`wb_uart16550_bus32_big`
193			`TB.test.dut`
194
195
196
197			`icaruscoverage`
198
199
200
201
202
203
204
205
206
207
208			`wb_uart16550_def_lint`
209			`def_lint`
210
211			`rtl_check`
212
213
214
215
216
217
218
219			`wb_uart16550_bus16_lit_lint`
220			`bus16_lit_lint`
221
222			`rtl_check`
223
224
225
226
227
228
229
230			`wb_uart16550_bus16_big_lint`
231			`bus16_big_lint`
232
233			`rtl_check`
234
235
236
237
238
239
240
241			`wb_uart16550_bus32_lit_lint`
242			`bus32_lit_lint`
243
244			`rtl_check`
245
246
247
248
249
250			`wb_uart16550_bus32_big_lint`
251			`bus32_big_lint`
252
253			`rtl_check`
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270			`default`
271			`wb_uart16550_def_lint`
272			`default`
273
274
275
276
277
278
279			`bus16_lit_default`
280			`wb_uart16550_bus16_lit_lint`
281			`default`
282
283
284
285
286			`bus16_big_default`
287			`wb_uart16550_bus16_big_lint`
288			`default`
289
290
291
292
293
294
295			`bus32_lit_default`
296			`wb_uart16550_bus32_lit_lint`
297			`default`
298
299
300
301
302
303			`bus32_big_default`
304			`wb_uart16550_bus32_big_lint`
305			`default`
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322			`default`
323			`wb_uart16550_def_tb`
324			`default`
325
326
327
328
329
330
331			`bus16_lit_default`
332			`wb_uart16550_bus16_lit_tb`
333	134	jt_eaton	`bus16`
334	131	jt_eaton
335
336
337
338			`bus16_big_default`
339			`wb_uart16550_bus16_big_tb`
340	134	jt_eaton	`bus16`
341	131	jt_eaton
342
343
344
345
346
347			`bus32_lit_default`
348			`wb_uart16550_bus32_lit_tb`
349	134	jt_eaton	`bus32`
350	131	jt_eaton
351
352
353
354
355			`bus32_big_default`
356			`wb_uart16550_bus32_big_tb`
357	134	jt_eaton	`bus32`
358	131	jt_eaton
359
360
361
362
363
364
365
366
367
368
369
370