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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_defines.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Defines of the Core                                         ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None                                                        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// 2011/10/01  Split into 8 bit and 32 bit versions
//             always provide baudrate output enable
//             converted PRESCALER_PRESET from `define to parameter
//             Removed unused `defines, added back LITTLE_ENDIAN
//             Removed all # delays for non-blocking statement
//             Changed all module names to start with `VARIANT
//             Converted reset from async to sync
//             jt_eaton
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13  2003/06/11 16:37:47  gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.12  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//
// Revision 1.10  2001/12/11 08:55:40  mohor
// Scratch register define added.
//
// Revision 1.9  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.8  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.7  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.6  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.5  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.4  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.3  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
//
//
 
 
// Interrupt Enable register bits
`define UART_IE_RDA     0        // Received Data available interrupt
`define UART_IE_THRE    1       // Transmitter Holding Register empty interrupt
`define UART_IE_RLS     2       // Receiver Line Status Interrupt
`define UART_IE_MS      3       // Modem Status Interrupt
 
// Interrupt Identification register bits
`define UART_II_IP      0        // Interrupt pending when 0
`define UART_II_II      3:1     // Interrupt identification
 
// Interrupt identification values for bits 3:1
`define UART_II_RLS     3'b011  // Receiver Line Status
`define UART_II_RDA     3'b010  // Receiver Data available
`define UART_II_TI      3'b110  // Timeout Indication
`define UART_II_THRE    3'b001  // Transmitter Holding Register empty
`define UART_II_MS      3'b000  // Modem Status
 
// FIFO Control Register bits
`define UART_FC_TL      7:6     // Trigger level
 
// FIFO trigger level values
`define UART_FC_1               2'b00
`define UART_FC_4               2'b01
`define UART_FC_8               2'b10
`define UART_FC_14              2'b11
 
// Line Control register bits
`define UART_LC_BITS    1:0     // bits in character
`define UART_LC_SB      2       // stop bits
`define UART_LC_PE      3       // parity enable
`define UART_LC_EP      4       // even parity
`define UART_LC_SP      5       // stick parity
`define UART_LC_BC      6       // Break control
`define UART_LC_DL      7       // Divisor Latch access bit
 
// Modem Control register bits
`define UART_MC_DTR     0
`define UART_MC_RTS     1
`define UART_MC_OUT1    2
`define UART_MC_OUT2    3
`define UART_MC_LB      4       // Loopback mode
 
// Line Status Register bits
`define UART_LS_DR      0        // Data ready
`define UART_LS_OE      1       // Overrun Error
`define UART_LS_PE      2       // Parity Error
`define UART_LS_FE      3       // Framing Error
`define UART_LS_BI      4       // Break interrupt
`define UART_LS_TFE     5       // Transmit FIFO is empty
`define UART_LS_TE      6       // Transmitter Empty indicator
`define UART_LS_EI      7       // Error indicator
 
// Modem Status Register bits
`define UART_MS_DCTS    0        // Delta signals
`define UART_MS_DDSR    1
`define UART_MS_TERI    2
`define UART_MS_DDCD    3
`define UART_MS_CCTS    4       // Complement signals
`define UART_MS_CDSR    5
`define UART_MS_CRI     6
`define UART_MS_CDCD    7
 
// FIFO parameter defines
 
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W     4
`define UART_FIFO_COUNTER_W     5
// receiver fifo has width 11 because it has break, parity and framing error bits
`define UART_FIFO_REC_WIDTH  11
 
 
 
 
// Defines hard baud prescaler register - uncomment to enable
//`define PRESCALER_PRESET_HARD
// 115200 baud preset values
// 20MHz: prescaler 10.8 (11, rounded up)
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd11
// 50MHz: prescaler 27.1
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd27

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [defines] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// Defines of the Core ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Nothing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29			`//// - Igor Mohor (igorm@opencores.org) ////`
30			`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000, 2001 Authors ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62
63			`// 2011/10/01 Split into 8 bit and 32 bit versions`
64			`// always provide baudrate output enable`
65			// converted PRESCALER_PRESET from `define to parameter
66			// Removed unused `defines, added back LITTLE_ENDIAN
67			`// Removed all # delays for non-blocking statement`
68			// Changed all module names to start with `VARIANT
69			`// Converted reset from async to sync`
70			`// jt_eaton`
71			`//`
72			`// CVS Revision History`
73			`//`
74			`// $Log: not supported by cvs2svn $`
75			`// Revision 1.13 2003/06/11 16:37:47 gorban`
76			`// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.`
77			`//`
78			`// Revision 1.12 2002/07/22 23:02:23 gorban`
79			`// Bug Fixes:`
80			`// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.`
81			`// Problem reported by Kenny.Tung.`
82			`// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.`
83			`//`
84			`// Improvements:`
85			`// * Made FIFO's as general inferrable memory where possible.`
86			`// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).`
87			`// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.`
88			`//`
89			`//`
90			`// Revision 1.10 2001/12/11 08:55:40 mohor`
91			`// Scratch register define added.`
92			`//`
93			`// Revision 1.9 2001/12/03 21:44:29 gorban`
94			`// Updated specification documentation.`
95			`// Added full 32-bit data bus interface, now as default.`
96			`// Address is 5-bit wide in 32-bit data bus mode.`
97			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
98			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
99			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
100			`// My small test bench is modified to work with 32-bit mode.`
101			`//`
102			`// Revision 1.8 2001/11/26 21:38:54 gorban`
103			`// Lots of fixes:`
104			`// Break condition wasn't handled correctly at all.`
105			`// LSR bits could lose their values.`
106			`// LSR value after reset was wrong.`
107			`// Timing of THRE interrupt signal corrected.`
108			`// LSR bit 0 timing corrected.`
109			`//`
110			`// Revision 1.7 2001/08/24 21:01:12 mohor`
111			`// Things connected to parity changed.`
112			`// Clock devider changed.`
113			`//`
114			`// Revision 1.6 2001/08/23 16:05:05 mohor`
115			`// Stop bit bug fixed.`
116			`// Parity bug fixed.`
117			`// WISHBONE read cycle bug fixed,`
118			`// OE indicator (Overrun Error) bug fixed.`
119			`// PE indicator (Parity Error) bug fixed.`
120			`// Register read bug fixed.`
121			`//`
122			`// Revision 1.5 2001/05/31 20:08:01 gorban`
123			`// FIFO changes and other corrections.`
124			`//`
125			`// Revision 1.4 2001/05/21 19:12:02 gorban`
126			`// Corrected some Linter messages.`
127			`//`
128			`// Revision 1.3 2001/05/17 18:34:18 gorban`
129			`// First 'stable' release. Should be sythesizable now. Also added new header.`
130			`//`
131			`// Revision 1.0 2001-05-17 21:27:11+02 jacob`
132			`// Initial revision`
133			`//`
134			`//`
135
136
137			`// Interrupt Enable register bits`
138			`define UART_IE_RDA 0 // Received Data available interrupt
139			`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
140			`define UART_IE_RLS 2 // Receiver Line Status Interrupt
141			`define UART_IE_MS 3 // Modem Status Interrupt
142
143			`// Interrupt Identification register bits`
144			`define UART_II_IP 0 // Interrupt pending when 0
145			`define UART_II_II 3:1 // Interrupt identification
146
147			`// Interrupt identification values for bits 3:1`
148			`define UART_II_RLS 3'b011 // Receiver Line Status
149			`define UART_II_RDA 3'b010 // Receiver Data available
150			`define UART_II_TI 3'b110 // Timeout Indication
151			`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
152			`define UART_II_MS 3'b000 // Modem Status
153
154			`// FIFO Control Register bits`
155			`define UART_FC_TL 7:6 // Trigger level
156
157			`// FIFO trigger level values`
158			`define UART_FC_1 2'b00
159			`define UART_FC_4 2'b01
160			`define UART_FC_8 2'b10
161			`define UART_FC_14 2'b11
162
163			`// Line Control register bits`
164			`define UART_LC_BITS 1:0 // bits in character
165			`define UART_LC_SB 2 // stop bits
166			`define UART_LC_PE 3 // parity enable
167			`define UART_LC_EP 4 // even parity
168			`define UART_LC_SP 5 // stick parity
169			`define UART_LC_BC 6 // Break control
170			`define UART_LC_DL 7 // Divisor Latch access bit
171
172			`// Modem Control register bits`
173			`define UART_MC_DTR 0
174			`define UART_MC_RTS 1
175			`define UART_MC_OUT1 2
176			`define UART_MC_OUT2 3
177			`define UART_MC_LB 4 // Loopback mode
178
179			`// Line Status Register bits`
180			`define UART_LS_DR 0 // Data ready
181			`define UART_LS_OE 1 // Overrun Error
182			`define UART_LS_PE 2 // Parity Error
183			`define UART_LS_FE 3 // Framing Error
184			`define UART_LS_BI 4 // Break interrupt
185			`define UART_LS_TFE 5 // Transmit FIFO is empty
186			`define UART_LS_TE 6 // Transmitter Empty indicator
187			`define UART_LS_EI 7 // Error indicator
188
189			`// Modem Status Register bits`
190			`define UART_MS_DCTS 0 // Delta signals
191			`define UART_MS_DDSR 1
192			`define UART_MS_TERI 2
193			`define UART_MS_DDCD 3
194			`define UART_MS_CCTS 4 // Complement signals
195			`define UART_MS_CDSR 5
196			`define UART_MS_CRI 6
197			`define UART_MS_CDCD 7
198
199			`// FIFO parameter defines`
200
201			`define UART_FIFO_WIDTH 8
202			`define UART_FIFO_DEPTH 16
203			`define UART_FIFO_POINTER_W 4
204			`define UART_FIFO_COUNTER_W 5
205			`// receiver fifo has width 11 because it has break, parity and framing error bits`
206			`define UART_FIFO_REC_WIDTH 11
207
208
209
210
211			`// Defines hard baud prescaler register - uncomment to enable`
212			//`define PRESCALER_PRESET_HARD
213			`// 115200 baud preset values`
214			`// 20MHz: prescaler 10.8 (11, rounded up)`
215			//`define PRESCALER_HIGH_PRESET 8'd0
216			//`define PRESCALER_LOW_PRESET 8'd11
217			`// 50MHz: prescaler 27.1`
218			//`define PRESCALER_HIGH_PRESET 8'd0
219			//`define PRESCALER_LOW_PRESET 8'd27