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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [top.body] - Blame information for rev 134

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   wire [7:0]                      rb_dll_rdata;
   wire [7:0]                      ie_dlh_rdata;
   wire [7:0]                      tr_reg_wdata;
   wire [3:0]                      ie_reg_wdata;
   wire [15:0]                     dl_reg_wdata;
   wire [7:0]                      scratch;
   wire [3:0]                      ier;
   wire [3:0]                      iir;
   wire [7:0]                      fcr;
   wire [4:0]                      mcr;
   wire [7:0]                      lcr;
   wire [7:0]                      msr;
   wire [7:0]                      lsr;
   wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
   wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
   wire [2:0]                      tstate;
   wire [3:0]                      rstate;
 
   wire                            we_o;
   wire                            re_o;
   wire                            tr_reg_wr;
   wire                            rb_dll_reg_dec;
   wire                            ls_reg_dec;
   wire                            ms_reg_dec;
   wire                            ii_reg_dec;
   wire                            ie_reg_wr;
 
 
   `VARIANT`WB_FSM  wb_interface
     (
      .clk         ( wb_clk_i    ),
      .wb_rst_i    ( wb_rst_i    ),
      .wb_we_i     ( wb_we_i     ),
      .wb_stb_i    ( wb_stb_i    ),
      .wb_cyc_i    ( wb_cyc_i    ),
      .wb_ack_o    ( wb_ack_o    ),
      .we_o        ( we_o        ),
      .re_o        ( re_o        )
      );
 
 
 
 
 
 `VARIANT`WB
#(.LC_REG_RST(8'b00000011),
  .II_REG_PAD(4'b1100),
  .FC_REG_RST(8'b11000000)
)
 micro_reg (
            .clk              ( wb_clk_i           ),
            .reset            ( wb_rst_i           ),
            .enable           (1'b1                ),
            .cs               ( wb_cyc_i           ),
            .wr               ( wb_we_i            ),
            .rd               (~wb_we_i            ),
            .addr             ( wb_adr_i           ),
            .byte_lanes       ( wb_sel_i           ),
            .wdata            ( wb_dat_i           ),
            .rdata            ( wb_dat_o           ),
            .rb_dll_reg_rdata ( rb_dll_rdata       ),
            .rb_dll_reg_dec   ( rb_dll_reg_dec     ),
            .tr_reg_wr_0      ( tr_reg_wr          ),
            .tr_reg_wdata     ( tr_reg_wdata       ),
            .dll_reg_wdata    ( dl_reg_wdata[7:0]  ),
            .dlh_reg_wdata    ( dl_reg_wdata[15:8] ),
            .ls_reg_dec       ( ls_reg_dec         ),
            .ms_reg_dec       ( ms_reg_dec         ),
            .ii_reg_dec       ( ii_reg_dec         ),
            .ie_dlh_reg_rdata ( ie_dlh_rdata       ),
            .ie_reg_wr_0      ( ie_reg_wr          ),
            .ie_reg_wdata     ( ie_reg_wdata       ),
            .ii_reg_rdata     ( iir                ),
            .fc_reg           ( fcr                ),
            .next_fc_reg      ( {fcr[7:6],6'h00}   ),
            .lc_reg           ( lcr                ),
            .lc_reg_rdata     ( lcr                ),
            .next_lc_reg      ( lcr                ),
            .mc_reg           ( mcr                ),
            .mc_reg_rdata     ( mcr                ),
            .next_mc_reg      ( mcr                ),
            .ls_reg_rdata     ( lsr                ),
            .ms_reg_rdata     ( msr                ),
            .sr_reg           ( scratch            ),
            .sr_reg_rdata     ( scratch            ),
            .next_sr_reg      ( scratch            ),
            .rb_dll_reg_cs    (                    ),
            .tr_reg_cs        (                    ),
            .tr_reg_dec       (                    ),
            .ie_dlh_reg_cs    (                    ),
            .ie_dlh_reg_dec   (                    ),
            .ie_reg_cs        (                    ),
            .ie_reg_dec       (                    ),
            .dll_reg_cs       (                    ),
            .dll_reg_dec      (                    ),
            .dll_reg_wr_0     (                    ),
            .dlh_reg_cs       (                    ),
            .dlh_reg_dec      (                    ),
            .dlh_reg_wr_0     (                    ),
            .ii_reg_cs        (                    ),
            .fc_reg_cs        (                    ),
            .fc_reg_dec       (                    ),
            .fc_reg_wr_0      (                    ),
            .lc_reg_cs        (                    ),
            .lc_reg_dec       (                    ),
            .lc_reg_wr_0      (                    ),
            .mc_reg_cs        (                    ),
            .mc_reg_dec       (                    ),
            .mc_reg_wr_0      (                    ),
            .ls_reg_cs        (                    ),
            .ms_reg_cs        (                    ),
            .sr_reg_cs        (                    ),
            .sr_reg_dec       (                    ),
            .sr_reg_wr_0      (                    ),
            .debug_0_reg_cs   (                    ),
            .debug_0_reg_dec  (                    ),
            .debug_1_reg_cs   (                    ),
            .debug_1_reg_dec  (                    ),
            .debug_0_reg_rdata ({msr,lcr,iir,ier,lsr}),
            .debug_1_reg_rdata ({8'b0, fcr[7:6],mcr, rf_count, rstate, tf_count, tstate})
);
 
 
 
 
 
 
   `VARIANT`REGS
     #(.PRESCALER_PRESET(PRESCALER_PRESET))
    regs
     (
      .clk           ( wb_clk_i       ),
      .wb_rst_i      ( wb_rst_i       ),
      .wb_we_i       ( we_o           ),
      .wb_re_i       ( re_o           ),
      .wb_dat_i      ( dl_reg_wdata   ),
      .tr_reg_wr     ( tr_reg_wr      ),
      .tr_reg_wdata  ( tr_reg_wdata   ),
      .rb_dll_reg_rd ( rb_dll_reg_dec ),
      .rdata_rb_dll  ( rb_dll_rdata   ),
      .rdata_ie_dlh  ( ie_dlh_rdata   ),
      .ls_reg_rd     ( ls_reg_dec     ),
      .ms_reg_rd     ( ms_reg_dec     ),
      .ii_reg_rd     ( ii_reg_dec     ),
      .ie_reg_wr     ( ie_reg_wr      ),
      .ie_reg_wdata  ( ie_reg_wdata   ),
      .cts_pad_i     ( cts_pad_i      ),
      .dsr_pad_i     ( dsr_pad_i      ),
      .ri_pad_i      ( ri_pad_i       ),
      .dcd_pad_i     ( dcd_pad_i      ),
      .stx_pad_o     ( stx_pad_o      ),
      .srx_pad_i     ( srx_pad_i      ),
      .ier           ( ier            ),
      .iir           ( iir            ),
      .fcr           ( fcr            ),
      .lcr           ( lcr            ),
      .msr           ( msr            ),
      .lsr           ( lsr            ),
      .mcr           ( mcr            ),
      .rf_count      ( rf_count       ),
      .tf_count      ( tf_count       ),
      .tstate        ( tstate         ),
      .rstate        ( rstate         ),
      .rts_pad_o     ( rts_pad_o      ),
      .dtr_pad_o     ( dtr_pad_o      ),
      .int_o         ( int_o          ),
      .baud_o        ( baud_o         )
      );
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`wire [7:0] rb_dll_rdata;`
3			`wire [7:0] ie_dlh_rdata;`
4			`wire [7:0] tr_reg_wdata;`
5			`wire [3:0] ie_reg_wdata;`
6			`wire [15:0] dl_reg_wdata;`
7			`wire [7:0] scratch;`
8			`wire [3:0] ier;`
9			`wire [3:0] iir;`
10			`wire [7:0] fcr;`
11			`wire [4:0] mcr;`
12			`wire [7:0] lcr;`
13			`wire [7:0] msr;`
14			`wire [7:0] lsr;`
15			wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
16			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
17			`wire [2:0] tstate;`
18			`wire [3:0] rstate;`
19
20			`wire we_o;`
21			`wire re_o;`
22			`wire tr_reg_wr;`
23			`wire rb_dll_reg_dec;`
24			`wire ls_reg_dec;`
25			`wire ms_reg_dec;`
26			`wire ii_reg_dec;`
27			`wire ie_reg_wr;`
28
29
30			`VARIANT`WB_FSM wb_interface
31			`(`
32			`.clk ( wb_clk_i ),`
33			`.wb_rst_i ( wb_rst_i ),`
34			`.wb_we_i ( wb_we_i ),`
35			`.wb_stb_i ( wb_stb_i ),`
36			`.wb_cyc_i ( wb_cyc_i ),`
37			`.wb_ack_o ( wb_ack_o ),`
38			`.we_o ( we_o ),`
39			`.re_o ( re_o )`
40			`);`
41
42
43
44
45
46			`VARIANT`WB
47			`#(.LC_REG_RST(8'b00000011),`
48			`.II_REG_PAD(4'b1100),`
49			`.FC_REG_RST(8'b11000000)`
50			`)`
51			`micro_reg (`
52			`.clk ( wb_clk_i ),`
53			`.reset ( wb_rst_i ),`
54			`.enable (1'b1 ),`
55			`.cs ( wb_cyc_i ),`
56			`.wr ( wb_we_i ),`
57			`.rd (~wb_we_i ),`
58			`.addr ( wb_adr_i ),`
59			`.byte_lanes ( wb_sel_i ),`
60			`.wdata ( wb_dat_i ),`
61			`.rdata ( wb_dat_o ),`
62			`.rb_dll_reg_rdata ( rb_dll_rdata ),`
63			`.rb_dll_reg_dec ( rb_dll_reg_dec ),`
64			`.tr_reg_wr_0 ( tr_reg_wr ),`
65			`.tr_reg_wdata ( tr_reg_wdata ),`
66			`.dll_reg_wdata ( dl_reg_wdata[7:0] ),`
67			`.dlh_reg_wdata ( dl_reg_wdata[15:8] ),`
68			`.ls_reg_dec ( ls_reg_dec ),`
69			`.ms_reg_dec ( ms_reg_dec ),`
70			`.ii_reg_dec ( ii_reg_dec ),`
71			`.ie_dlh_reg_rdata ( ie_dlh_rdata ),`
72			`.ie_reg_wr_0 ( ie_reg_wr ),`
73			`.ie_reg_wdata ( ie_reg_wdata ),`
74			`.ii_reg_rdata ( iir ),`
75			`.fc_reg ( fcr ),`
76			`.next_fc_reg ( {fcr[7:6],6'h00} ),`
77			`.lc_reg ( lcr ),`
78			`.lc_reg_rdata ( lcr ),`
79			`.next_lc_reg ( lcr ),`
80			`.mc_reg ( mcr ),`
81			`.mc_reg_rdata ( mcr ),`
82			`.next_mc_reg ( mcr ),`
83			`.ls_reg_rdata ( lsr ),`
84			`.ms_reg_rdata ( msr ),`
85			`.sr_reg ( scratch ),`
86			`.sr_reg_rdata ( scratch ),`
87			`.next_sr_reg ( scratch ),`
88			`.rb_dll_reg_cs ( ),`
89			`.tr_reg_cs ( ),`
90			`.tr_reg_dec ( ),`
91			`.ie_dlh_reg_cs ( ),`
92			`.ie_dlh_reg_dec ( ),`
93			`.ie_reg_cs ( ),`
94			`.ie_reg_dec ( ),`
95			`.dll_reg_cs ( ),`
96			`.dll_reg_dec ( ),`
97			`.dll_reg_wr_0 ( ),`
98			`.dlh_reg_cs ( ),`
99			`.dlh_reg_dec ( ),`
100			`.dlh_reg_wr_0 ( ),`
101			`.ii_reg_cs ( ),`
102			`.fc_reg_cs ( ),`
103			`.fc_reg_dec ( ),`
104			`.fc_reg_wr_0 ( ),`
105			`.lc_reg_cs ( ),`
106			`.lc_reg_dec ( ),`
107			`.lc_reg_wr_0 ( ),`
108			`.mc_reg_cs ( ),`
109			`.mc_reg_dec ( ),`
110			`.mc_reg_wr_0 ( ),`
111			`.ls_reg_cs ( ),`
112			`.ms_reg_cs ( ),`
113			`.sr_reg_cs ( ),`
114			`.sr_reg_dec ( ),`
115			`.sr_reg_wr_0 ( ),`
116			`.debug_0_reg_cs ( ),`
117			`.debug_0_reg_dec ( ),`
118			`.debug_1_reg_cs ( ),`
119			`.debug_1_reg_dec ( ),`
120			`.debug_0_reg_rdata ({msr,lcr,iir,ier,lsr}),`
121			`.debug_1_reg_rdata ({8'b0, fcr[7:6],mcr, rf_count, rstate, tf_count, tstate})`
122			`);`
123
124
125
126
127
128
129			`VARIANT`REGS
130			`#(.PRESCALER_PRESET(PRESCALER_PRESET))`
131			`regs`
132			`(`
133			`.clk ( wb_clk_i ),`
134			`.wb_rst_i ( wb_rst_i ),`
135			`.wb_we_i ( we_o ),`
136			`.wb_re_i ( re_o ),`
137			`.wb_dat_i ( dl_reg_wdata ),`
138			`.tr_reg_wr ( tr_reg_wr ),`
139			`.tr_reg_wdata ( tr_reg_wdata ),`
140			`.rb_dll_reg_rd ( rb_dll_reg_dec ),`
141			`.rdata_rb_dll ( rb_dll_rdata ),`
142			`.rdata_ie_dlh ( ie_dlh_rdata ),`
143			`.ls_reg_rd ( ls_reg_dec ),`
144			`.ms_reg_rd ( ms_reg_dec ),`
145			`.ii_reg_rd ( ii_reg_dec ),`
146			`.ie_reg_wr ( ie_reg_wr ),`
147			`.ie_reg_wdata ( ie_reg_wdata ),`
148			`.cts_pad_i ( cts_pad_i ),`
149			`.dsr_pad_i ( dsr_pad_i ),`
150			`.ri_pad_i ( ri_pad_i ),`
151			`.dcd_pad_i ( dcd_pad_i ),`
152			`.stx_pad_o ( stx_pad_o ),`
153			`.srx_pad_i ( srx_pad_i ),`
154			`.ier ( ier ),`
155			`.iir ( iir ),`
156			`.fcr ( fcr ),`
157			`.lcr ( lcr ),`
158			`.msr ( msr ),`
159			`.lsr ( lsr ),`
160			`.mcr ( mcr ),`
161			`.rf_count ( rf_count ),`
162			`.tf_count ( tf_count ),`
163			`.tstate ( tstate ),`
164			`.rstate ( rstate ),`
165			`.rts_pad_o ( rts_pad_o ),`
166			`.dtr_pad_o ( dtr_pad_o ),`
167			`.int_o ( int_o ),`
168			`.baud_o ( baud_o )`
169			`);`
170
171
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [top.body] - Blame information for rev 134