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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [transmitter] - Blame information for rev 131

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//
// Revision 1.16  2002/01/08 11:29:40  mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
 
 
module `VARIANT`TRANSMITTER  (
      input  wire                                   clk,
      input  wire                                   wb_rst_i,
      input  wire  [7:0]                            lcr,
      input  wire                                   tf_push,
      input  wire  [7:0]                            tf_data_in,
      input  wire                                   enable,
      input  wire                                   tx_reset,
      input  wire                                   lsr_mask,
 
      output wire                                   stx_pad_o,
      output  reg [2:0]                             tstate,
      output wire [`UART_FIFO_COUNTER_W-1:0]        tf_count
     );
 
 
 
 
reg [4:0]                                  counter;
reg [2:0]                                  bit_counter;   // counts the bits to be sent
reg [6:0]                                  shift_out;     // output shift register
reg                                        stx_o_tmp;
reg                                        parity_xor;  // parity of the word
reg                                        tf_pop;
reg                                        bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0]                tf_data_out;
wire                                       tf_overrun;
 
 
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
 
`VARIANT`TFIFO  fifo_tx(     // error bit signal is not used in transmitter FIFO
     .clk           ( clk         ),
     .wb_rst_i      ( wb_rst_i    ),
     .data_in       ( tf_data_in  ),
     .data_out      ( tf_data_out ),
     .push          ( tf_push     ),
     .pop           ( tf_pop      ),
     .overrun       ( tf_overrun  ),
     .count         ( tf_count    ),
     .fifo_reset    ( tx_reset    ),
     .reset_status  ( lsr_mask    )
);
 
 
 
 
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk )
begin
  if (wb_rst_i)
  begin
     tstate       <=  s_idle;
     stx_o_tmp       <=  1'b1;
     counter   <=  5'b0;
     shift_out   <=  7'b0;
     bit_out     <=  1'b0;
     parity_xor  <=  1'b0;
     tf_pop      <=  1'b0;
     bit_counter <=  3'b0;
  end
  else
  if (enable)
  begin
     case (tstate)
     s_idle      :     if (~|tf_count) // if tf_count==0
               begin
                    tstate <=  s_idle;
                    stx_o_tmp <=  1'b1;
               end
               else
               begin
                    tf_pop <=  1'b0;
                    stx_o_tmp  <=  1'b1;
                    tstate  <=  s_pop_byte;
               end
     s_pop_byte :     begin
                    tf_pop <=  1'b1;
                    case (lcr[1:0])  // number of bits in a word
                    2'b00 : begin
                         bit_counter <=  3'b100;
                         parity_xor  <=  ^tf_data_out[4:0];
                         end
                    2'b01 : begin
                         bit_counter <=  3'b101;
                         parity_xor  <=  ^tf_data_out[5:0];
                         end
                    2'b10 : begin
                         bit_counter <=  3'b110;
                         parity_xor  <=  ^tf_data_out[6:0];
                         end
                    2'b11 : begin
                         bit_counter <=  3'b111;
                         parity_xor  <=  ^tf_data_out[7:0];
                         end
                    endcase
                    {shift_out[6:0], bit_out} <=  tf_data_out;
                    tstate <=  s_send_start;
               end
     s_send_start :     begin
                    tf_pop <=  1'b0;
                    if (~|counter)
                         counter <=  5'b01111;
                    else
                    if (counter == 5'b00001)
                    begin
                         counter <=  0;
                         tstate <=  s_send_byte;
                    end
                    else
                         counter <=  counter - 5'd1;
                    stx_o_tmp <=  1'b0;
               end
     s_send_byte :     begin
                    if (~|counter)
                         counter <=  5'b01111;
                    else
                    if (counter == 5'b00001)
                    begin
                         if (bit_counter > 3'b0)
                         begin
                              bit_counter <=  bit_counter - 3'd1;
                              {shift_out[5:0],bit_out  } <=  {shift_out[6:1], shift_out[0]};
                              tstate <=  s_send_byte;
                         end
                         else   // end of byte
                         if (~lcr[`UART_LC_PE])
                         begin
                              tstate <=  s_send_stop;
                         end
                         else
                         begin
                              case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                              2'b00:     bit_out <=  ~parity_xor;
                              2'b01:     bit_out <=  1'b1;
                              2'b10:     bit_out <=  parity_xor;
                              2'b11:     bit_out <=  1'b0;
                              endcase
                              tstate <=  s_send_parity;
                         end
                         counter <=  0;
                    end
                    else
                         counter <=  counter - 5'd1;
                    stx_o_tmp <=  bit_out; // set output pin
               end
     s_send_parity :     begin
                    if (~|counter)
                         counter <=  5'b01111;
                    else
                    if (counter == 5'b00001)
                    begin
                         counter <=  5'd0;
                         tstate <=  s_send_stop;
                    end
                    else
                         counter <=  counter - 5'd1;
                    stx_o_tmp <=  bit_out;
               end
     s_send_stop :  begin
                    if (~|counter)
                      begin
                              casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                3'b0??:       counter <=  5'b01101;     // 1 stop bit ok igor
                                3'b100:       counter <=  5'b10101;     // 1.5 stop bit
                                default:       counter <=  5'b11101;     // 2 stop bits
                              endcase
                         end
                    else
                    if (counter == 5'b00001)
                    begin
                         counter <=  0;
                         tstate <=  s_idle;
                    end
                    else
                         counter <=  counter - 5'd1;
                    stx_o_tmp <=  1'b1;
               end
 
          default : // should never get here
               tstate <=  s_idle;
     endcase
  end // end if enable
  else
    tf_pop <=  1'b0;  // tf_pop must be 1 cycle width
end // transmitter logic
 
 
 
endmodule

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [transmitter] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29			`//// - Igor Mohor (igorm@opencores.org) ////`
30			`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000, 2001 Authors ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.18 2002/07/22 23:02:23 gorban`
67			`// Bug Fixes:`
68			`// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.`
69			`// Problem reported by Kenny.Tung.`
70			`// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.`
71			`//`
72			`// Improvements:`
73			`// * Made FIFO's as general inferrable memory where possible.`
74			`// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).`
75			`// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.`
76			`//`
77			`//`
78			`// Revision 1.16 2002/01/08 11:29:40 mohor`
79			`// tf_pop was too wide. Now it is only 1 clk cycle width.`
80			`//`
81			`// Revision 1.15 2001/12/17 14:46:48 mohor`
82			`// overrun signal was moved to separate block because many sequential lsr`
83			`// reads were preventing data from being written to rx fifo.`
84			`// underrun signal was not used and was removed from the project.`
85			`//`
86			`// Revision 1.14 2001/12/03 21:44:29 gorban`
87			`// Updated specification documentation.`
88			`// Added full 32-bit data bus interface, now as default.`
89			`// Address is 5-bit wide in 32-bit data bus mode.`
90			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
91			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
92			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
93			`// My small test bench is modified to work with 32-bit mode.`
94			`//`
95			`// Revision 1.13 2001/11/08 14:54:23 mohor`
96			`// Comments in Slovene language deleted, few small fixes for better work of`
97			`// old tools. IRQs need to be fix.`
98			`//`
99			`// Revision 1.12 2001/11/07 17:51:52 gorban`
100			`// Heavily rewritten interrupt and LSR subsystems.`
101			`// Many bugs hopefully squashed.`
102			`//`
103			`// Revision 1.11 2001/10/29 17:00:46 gorban`
104			`// fixed parity sending and tx_fifo resets over- and underrun`
105			`//`
106			`// Revision 1.10 2001/10/20 09:58:40 gorban`
107			`// Small synopsis fixes`
108			`//`
109			`// Revision 1.9 2001/08/24 21:01:12 mohor`
110			`// Things connected to parity changed.`
111			`// Clock devider changed.`
112			`//`
113			`// Revision 1.8 2001/08/23 16:05:05 mohor`
114			`// Stop bit bug fixed.`
115			`// Parity bug fixed.`
116			`// WISHBONE read cycle bug fixed,`
117			`// OE indicator (Overrun Error) bug fixed.`
118			`// PE indicator (Parity Error) bug fixed.`
119			`// Register read bug fixed.`
120			`//`
121			`// Revision 1.6 2001/06/23 11:21:48 gorban`
122			`// DL made 16-bit long. Fixed transmission/reception bugs.`
123			`//`
124			`// Revision 1.5 2001/06/02 14:28:14 gorban`
125			`// Fixed receiver and transmitter. Major bug fixed.`
126			`//`
127			`// Revision 1.4 2001/05/31 20:08:01 gorban`
128			`// FIFO changes and other corrections.`
129			`//`
130			`// Revision 1.3 2001/05/27 17:37:49 gorban`
131			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
132			`//`
133			`// Revision 1.2 2001/05/21 19:12:02 gorban`
134			`// Corrected some Linter messages.`
135			`//`
136			`// Revision 1.1 2001/05/17 18:34:18 gorban`
137			`// First 'stable' release. Should be sythesizable now. Also added new header.`
138			`//`
139			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
140			`// Initial revision`
141			`//`
142			`//`
143
144
145
146			module `VARIANT`TRANSMITTER (
147			`input wire clk,`
148			`input wire wb_rst_i,`
149			`input wire [7:0] lcr,`
150			`input wire tf_push,`
151			`input wire [7:0] tf_data_in,`
152			`input wire enable,`
153			`input wire tx_reset,`
154			`input wire lsr_mask,`
155
156			`output wire stx_pad_o,`
157			`output reg [2:0] tstate,`
158			output wire [`UART_FIFO_COUNTER_W-1:0] tf_count
159			`);`
160
161
162
163
164			`reg [4:0] counter;`
165			`reg [2:0] bit_counter; // counts the bits to be sent`
166			`reg [6:0] shift_out; // output shift register`
167			`reg stx_o_tmp;`
168			`reg parity_xor; // parity of the word`
169			`reg tf_pop;`
170			`reg bit_out;`
171
172			`// TX FIFO instance`
173			`//`
174			`// Transmitter FIFO signals`
175			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
176			`wire tf_overrun;`
177
178
179
180			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
181
182
183			`VARIANT`TFIFO fifo_tx( // error bit signal is not used in transmitter FIFO
184			`.clk ( clk ),`
185			`.wb_rst_i ( wb_rst_i ),`
186			`.data_in ( tf_data_in ),`
187			`.data_out ( tf_data_out ),`
188			`.push ( tf_push ),`
189			`.pop ( tf_pop ),`
190			`.overrun ( tf_overrun ),`
191			`.count ( tf_count ),`
192			`.fifo_reset ( tx_reset ),`
193			`.reset_status ( lsr_mask )`
194			`);`
195
196
197
198
199
200			`// TRANSMITTER FINAL STATE MACHINE`
201
202			`parameter s_idle = 3'd0;`
203			`parameter s_send_start = 3'd1;`
204			`parameter s_send_byte = 3'd2;`
205			`parameter s_send_parity = 3'd3;`
206			`parameter s_send_stop = 3'd4;`
207			`parameter s_pop_byte = 3'd5;`
208
209			`always @(posedge clk )`
210			`begin`
211			`if (wb_rst_i)`
212			`begin`
213			`tstate <= s_idle;`
214			`stx_o_tmp <= 1'b1;`
215			`counter <= 5'b0;`
216			`shift_out <= 7'b0;`
217			`bit_out <= 1'b0;`
218			`parity_xor <= 1'b0;`
219			`tf_pop <= 1'b0;`
220			`bit_counter <= 3'b0;`
221			`end`
222			`else`
223			`if (enable)`
224			`begin`
225			`case (tstate)`
226			`s_idle : if (~\|tf_count) // if tf_count==0`
227			`begin`
228			`tstate <= s_idle;`
229			`stx_o_tmp <= 1'b1;`
230			`end`
231			`else`
232			`begin`
233			`tf_pop <= 1'b0;`
234			`stx_o_tmp <= 1'b1;`
235			`tstate <= s_pop_byte;`
236			`end`
237			`s_pop_byte : begin`
238			`tf_pop <= 1'b1;`
239			`case (lcr[1:0]) // number of bits in a word`
240			`2'b00 : begin`
241			`bit_counter <= 3'b100;`
242			`parity_xor <= ^tf_data_out[4:0];`
243			`end`
244			`2'b01 : begin`
245			`bit_counter <= 3'b101;`
246			`parity_xor <= ^tf_data_out[5:0];`
247			`end`
248			`2'b10 : begin`
249			`bit_counter <= 3'b110;`
250			`parity_xor <= ^tf_data_out[6:0];`
251			`end`
252			`2'b11 : begin`
253			`bit_counter <= 3'b111;`
254			`parity_xor <= ^tf_data_out[7:0];`
255			`end`
256			`endcase`
257			`{shift_out[6:0], bit_out} <= tf_data_out;`
258			`tstate <= s_send_start;`
259			`end`
260			`s_send_start : begin`
261			`tf_pop <= 1'b0;`
262			`if (~\|counter)`
263			`counter <= 5'b01111;`
264			`else`
265			`if (counter == 5'b00001)`
266			`begin`
267			`counter <= 0;`
268			`tstate <= s_send_byte;`
269			`end`
270			`else`
271			`counter <= counter - 5'd1;`
272			`stx_o_tmp <= 1'b0;`
273			`end`
274			`s_send_byte : begin`
275			`if (~\|counter)`
276			`counter <= 5'b01111;`
277			`else`
278			`if (counter == 5'b00001)`
279			`begin`
280			`if (bit_counter > 3'b0)`
281			`begin`
282			`bit_counter <= bit_counter - 3'd1;`
283			`{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};`
284			`tstate <= s_send_byte;`
285			`end`
286			`else // end of byte`
287			if (~lcr[`UART_LC_PE])
288			`begin`
289			`tstate <= s_send_stop;`
290			`end`
291			`else`
292			`begin`
293			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
294			`2'b00: bit_out <= ~parity_xor;`
295			`2'b01: bit_out <= 1'b1;`
296			`2'b10: bit_out <= parity_xor;`
297			`2'b11: bit_out <= 1'b0;`
298			`endcase`
299			`tstate <= s_send_parity;`
300			`end`
301			`counter <= 0;`
302			`end`
303			`else`
304			`counter <= counter - 5'd1;`
305			`stx_o_tmp <= bit_out; // set output pin`
306			`end`
307			`s_send_parity : begin`
308			`if (~\|counter)`
309			`counter <= 5'b01111;`
310			`else`
311			`if (counter == 5'b00001)`
312			`begin`
313			`counter <= 5'd0;`
314			`tstate <= s_send_stop;`
315			`end`
316			`else`
317			`counter <= counter - 5'd1;`
318			`stx_o_tmp <= bit_out;`
319			`end`
320			`s_send_stop : begin`
321			`if (~\|counter)`
322			`begin`
323			casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
324			`3'b0??: counter <= 5'b01101; // 1 stop bit ok igor`
325			`3'b100: counter <= 5'b10101; // 1.5 stop bit`
326			`default: counter <= 5'b11101; // 2 stop bits`
327			`endcase`
328			`end`
329			`else`
330			`if (counter == 5'b00001)`
331			`begin`
332			`counter <= 0;`
333			`tstate <= s_idle;`
334			`end`
335			`else`
336			`counter <= counter - 5'd1;`
337			`stx_o_tmp <= 1'b1;`
338			`end`
339
340			`default : // should never get here`
341			`tstate <= s_idle;`
342			`endcase`
343			`end // end if enable`
344			`else`
345			`tf_pop <= 1'b0; // tf_pop must be 1 cycle width`
346			`end // transmitter logic`
347
348
349
350			`endmodule`