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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_big  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   big
   8
     
     
 
        
         adr
         
         wb_adr_i
           71
         
       
 
 
        
         wdata
         
         wb_dat_i
           150
         
       
 
 
        
         rdata
         
         wb_dat_o
           150
         
       
 
 
        
         sel
         
         wb_sel_i
           10
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 

  gen_registers
  103.0
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus16_big
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus16_big
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus16_big
        verilogSourcemodule
      
 
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width16
wb_byte_lanes2
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 

 

8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  16
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_big default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`big`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`71`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`150`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`150`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`10`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`gen_registers`
171			`103.0`
172			`none`
173			`common`
174			`./tools/regtool/gen_registers`
175
176
177			`bus_intf`
178			`wb`
179
180
181			`dest_dir`
182			`../verilog`
183
184
185
186
187
188
189
190
191			`gen_verilog`
192			`104.0`
193			`none`
194			`common`
195			`./tools/verilog/gen_verilog`
196
197
198			`destination`
199			`top.bus16_big`
200
201
202			`dest_dir`
203			`../verilog`
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219			`fs-common`
220
221
222
223			`../verilog/top.body`
224			`verilogSourcefragment`
225
226
227
228
229
230
231
232
233
234			`fs-sim`
235
236
237
238			`../verilog/copyright.v`
239			`verilogSourceinclude`
240
241
242
243
244
245			`../verilog/common/top.bus16_big`
246			`verilogSourcemodule`
247
248
249
250
251
252			`../verilog/defines`
253			`verilogSourceinclude`
254
255
256
257			`wb`
258			`../verilog/wb_uart16550_bus16_big_wb`
259			`verilogSourcemodule`
260
261
262
263
264			`raminfr`
265			`../verilog/raminfr`
266			`verilogSourcemodule`
267
268
269
270			`receiver`
271			`../verilog/receiver`
272			`verilogSourcemodule`
273
274
275
276			`regs`
277			`../verilog/regs`
278			`verilogSourcemodule`
279
280
281
282			`rfifo`
283			`../verilog/rfifo`
284			`verilogSourcemodule`
285
286
287
288			`sync_flops`
289			`../verilog/sync_flops`
290			`verilogSourcemodule`
291
292
293
294			`tfifo`
295			`../verilog/tfifo`
296			`verilogSourcemodule`
297
298
299
300			`transmitter`
301			`../verilog/transmitter`
302			`verilogSourcemodule`
303
304
305
306			`wb_fsm`
307			`../verilog/wb_fsm`
308			`verilogSourcemodule`
309
310
311
312			`dest_dir../views/sim/`
313			`verilogSourcelibraryDir`
314
315
316
317
318
319
320
321
322			`fs-syn`
323
324
325
326			`../verilog/copyright.v`
327			`verilogSourceinclude`
328
329
330
331
332
333			`../verilog/common/top.bus16_big`
334			`verilogSourcemodule`
335
336
337
338
339
340
341
342			`../verilog/defines`
343			`verilogSourceinclude`
344
345
346
347			`wb`
348			`../verilog/wb_uart16550_bus16_big_wb`
349			`verilogSourcemodule`
350
351
352
353
354			`raminfr`
355			`../verilog/raminfr`
356			`verilogSourcemodule`
357
358
359
360			`receiver`
361			`../verilog/receiver`
362			`verilogSourcemodule`
363
364
365
366			`regs`
367			`../verilog/regs`
368			`verilogSourcemodule`
369
370
371
372			`rfifo`
373			`../verilog/rfifo`
374			`verilogSourcemodule`
375
376
377
378			`sync_flops`
379			`../verilog/sync_flops`
380			`verilogSourcemodule`
381
382
383
384			`tfifo`
385			`../verilog/tfifo`
386			`verilogSourcemodule`
387
388
389
390			`transmitter`
391			`../verilog/transmitter`
392			`verilogSourcemodule`
393
394
395
396			`wb_fsm`
397			`../verilog/wb_fsm`
398			`verilogSourcemodule`
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415			`verilog`
416
417
418			`spirit:library="Testbench"`
419			`spirit:name="toolflow"`
420			`spirit:version="verilog"/>`
421
422
423
424
425
426
427
428
429
430			`commoncommon`
431
432			`Verilog`
433
434
435			`fs-common`
436
437
438
439
440			`sim:Simulation:`
441
442			`Verilog`
443
444
445			`fs-sim`
446
447
448
449
450			`syn:Synthesis:`
451
452			`Verilog`
453
454
455			`fs-syn`
456
457
458
459
460
461			`doc`
462
463
464			`spirit:library="Testbench"`
465			`spirit:name="toolflow"`
466			`spirit:version="documentation"/>`
467
468			`:Documentation:`
469			`Verilog`
470
471
472
473
474
475
476
477
478			`wb_addr_width8`
479			`wb_data_width16`
480			`wb_byte_lanes2`
481			`PRESCALER_PRESET16'h1234`
482
483
484
485
486
487			`baud_o`
488			`wire`
489			`out`
490
491
492			`cts_pad_i`
493			`wire`
494			`in`
495
496
497			`dcd_pad_i`
498			`wire`
499			`in`
500
501
502			`dsr_pad_i`
503			`wire`
504			`in`
505
506
507			`dtr_pad_o`
508			`wire`
509			`out`
510
511
512			`int_o`
513			`wire`
514			`out`
515
516
517
518			`ri_pad_i`
519			`wire`
520			`in`
521
522
523			`rts_pad_o`
524			`wire`
525			`out`
526
527
528			`srx_pad_i`
529			`wire`
530			`in`
531
532
533			`stx_pad_o`
534			`wire`
535			`out`
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550			`8`
551			`wb`
552
553			`wb`
554			`0x00`
555
556
557			`mb_microbus`
558			`0x100`
559			`16`
560
561
562
563			`rb_dll_reg`
564			`0x0`
565			`8`
566			`read-only`
567
568
569
570			`tr_reg`
571			`0x0`
572			`8`
573			`write-strobe`
574
575
576
577
578			`ie_dlh_reg`
579			`0x1`
580			`8`
581			`read-only`
582
583
584
585			`ie_reg`
586			`0x1`
587			`4`
588			`write-strobe`
589
590
591
592
593			`dll_reg`
594			`0x0`
595			`8`
596			`write-strobe`
597
598
599
600
601			`dlh_reg`
602			`0x1`
603			`8`
604			`write-strobe`
605
606
607
608
609
610			`ii_reg`
611			`0x2`
612			`4`
613			`read-only`
614
615
616
617			`fc_reg`
618			`0x2`
619			`8`
620			`write-only`
621
622
623
624
625			`lc_reg`
626			`0x3`
627			`8`
628			`read-write`
629
630
631
632			`mc_reg`
633			`0x4`
634			`5`
635			`read-write`
636
637
638
639			`ls_reg`
640			`0x5`
641			`8`
642			`read-only`
643
644
645
646			`ms_reg`
647			`0x6`
648			`8`
649			`read-only`
650
651
652
653			`sr_reg`
654			`0x7`
655			`8`
656			`read-write`
657
658
659
660
661			`debug_0_reg`
662			`0x8`
663			`32`
664			`read-only`
665
666
667
668
669			`debug_1_reg`
670			`0xc`
671			`32`
672			`read-only`
673
674
675
676
677
678
679
680
681
682
683
684
685
686