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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_big  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   big
   8
     
     
 
        
         adr
         
         wb_adr_i
           71
         
       
 
 
        
         wdata
         
         wb_dat_i
           150
         
       
 
 
        
         rdata
         
         wb_dat_o
           150
         
       
 
 
        
         sel
         
         wb_sel_i
           10
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus16_big
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus16_big
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus16_big
        verilogSourcemodule
      
 
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width16
wb_byte_lanes2
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 

 

8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  16
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_big default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`big`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`71`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`150`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`150`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`10`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170	133	jt_eaton	`elab_verilog`
171			`102.1`
172			`none`
173			`:Simulation:`
174			`./tools/verilog/elab_verilog`
175
176
177			`dest_dir`
178			`io_ports`
179
180
181
182
183
184
185
186
187	131	jt_eaton	`gen_registers`
188	133	jt_eaton	`102.1`
189	131	jt_eaton	`none`
190			`common`
191			`./tools/regtool/gen_registers`
192
193
194			`bus_intf`
195			`wb`
196
197
198			`dest_dir`
199			`../verilog`
200
201
202
203
204
205
206
207
208			`gen_verilog`
209			`104.0`
210			`none`
211			`common`
212			`./tools/verilog/gen_verilog`
213
214
215			`destination`
216			`top.bus16_big`
217
218
219			`dest_dir`
220			`../verilog`
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236			`fs-common`
237
238
239
240			`../verilog/top.body`
241			`verilogSourcefragment`
242
243
244
245
246
247
248
249
250
251			`fs-sim`
252
253
254
255			`../verilog/copyright.v`
256			`verilogSourceinclude`
257
258
259
260
261
262			`../verilog/common/top.bus16_big`
263			`verilogSourcemodule`
264
265
266
267
268
269			`../verilog/defines`
270			`verilogSourceinclude`
271
272
273
274			`wb`
275			`../verilog/wb_uart16550_bus16_big_wb`
276			`verilogSourcemodule`
277
278
279
280
281			`raminfr`
282			`../verilog/raminfr`
283			`verilogSourcemodule`
284
285
286
287			`receiver`
288			`../verilog/receiver`
289			`verilogSourcemodule`
290
291
292
293			`regs`
294			`../verilog/regs`
295			`verilogSourcemodule`
296
297
298
299			`rfifo`
300			`../verilog/rfifo`
301			`verilogSourcemodule`
302
303
304
305			`sync_flops`
306			`../verilog/sync_flops`
307			`verilogSourcemodule`
308
309
310
311			`tfifo`
312			`../verilog/tfifo`
313			`verilogSourcemodule`
314
315
316
317			`transmitter`
318			`../verilog/transmitter`
319			`verilogSourcemodule`
320
321
322
323			`wb_fsm`
324			`../verilog/wb_fsm`
325			`verilogSourcemodule`
326
327
328
329			`dest_dir../views/sim/`
330			`verilogSourcelibraryDir`
331
332
333
334
335
336
337
338
339			`fs-syn`
340
341
342
343			`../verilog/copyright.v`
344			`verilogSourceinclude`
345
346
347
348
349
350			`../verilog/common/top.bus16_big`
351			`verilogSourcemodule`
352
353
354
355
356
357
358
359			`../verilog/defines`
360			`verilogSourceinclude`
361
362
363
364			`wb`
365			`../verilog/wb_uart16550_bus16_big_wb`
366			`verilogSourcemodule`
367
368
369
370
371			`raminfr`
372			`../verilog/raminfr`
373			`verilogSourcemodule`
374
375
376
377			`receiver`
378			`../verilog/receiver`
379			`verilogSourcemodule`
380
381
382
383			`regs`
384			`../verilog/regs`
385			`verilogSourcemodule`
386
387
388
389			`rfifo`
390			`../verilog/rfifo`
391			`verilogSourcemodule`
392
393
394
395			`sync_flops`
396			`../verilog/sync_flops`
397			`verilogSourcemodule`
398
399
400
401			`tfifo`
402			`../verilog/tfifo`
403			`verilogSourcemodule`
404
405
406
407			`transmitter`
408			`../verilog/transmitter`
409			`verilogSourcemodule`
410
411
412
413			`wb_fsm`
414			`../verilog/wb_fsm`
415			`verilogSourcemodule`
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432			`verilog`
433
434
435			`spirit:library="Testbench"`
436			`spirit:name="toolflow"`
437			`spirit:version="verilog"/>`
438
439
440
441
442
443
444
445
446
447			`commoncommon`
448
449			`Verilog`
450
451
452			`fs-common`
453
454
455
456
457			`sim:Simulation:`
458
459			`Verilog`
460
461
462			`fs-sim`
463
464
465
466
467			`syn:Synthesis:`
468
469			`Verilog`
470
471
472			`fs-syn`
473
474
475
476
477
478			`doc`
479
480
481			`spirit:library="Testbench"`
482			`spirit:name="toolflow"`
483			`spirit:version="documentation"/>`
484
485			`:Documentation:`
486			`Verilog`
487
488
489
490
491
492
493
494
495			`wb_addr_width8`
496			`wb_data_width16`
497			`wb_byte_lanes2`
498			`PRESCALER_PRESET16'h1234`
499
500
501
502
503
504			`baud_o`
505			`wire`
506			`out`
507
508
509			`cts_pad_i`
510			`wire`
511			`in`
512
513
514			`dcd_pad_i`
515			`wire`
516			`in`
517
518
519			`dsr_pad_i`
520			`wire`
521			`in`
522
523
524			`dtr_pad_o`
525			`wire`
526			`out`
527
528
529			`int_o`
530			`wire`
531			`out`
532
533
534
535			`ri_pad_i`
536			`wire`
537			`in`
538
539
540			`rts_pad_o`
541			`wire`
542			`out`
543
544
545			`srx_pad_i`
546			`wire`
547			`in`
548
549
550			`stx_pad_o`
551			`wire`
552			`out`
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567			`8`
568			`wb`
569
570			`wb`
571			`0x00`
572
573
574			`mb_microbus`
575			`0x100`
576			`16`
577
578
579
580			`rb_dll_reg`
581			`0x0`
582			`8`
583			`read-only`
584
585
586
587			`tr_reg`
588			`0x0`
589			`8`
590			`write-strobe`
591
592
593
594
595			`ie_dlh_reg`
596			`0x1`
597			`8`
598			`read-only`
599
600
601
602			`ie_reg`
603			`0x1`
604			`4`
605			`write-strobe`
606
607
608
609
610			`dll_reg`
611			`0x0`
612			`8`
613			`write-strobe`
614
615
616
617
618			`dlh_reg`
619			`0x1`
620			`8`
621			`write-strobe`
622
623
624
625
626
627			`ii_reg`
628			`0x2`
629			`4`
630			`read-only`
631
632
633
634			`fc_reg`
635			`0x2`
636			`8`
637			`write-only`
638
639
640
641
642			`lc_reg`
643			`0x3`
644			`8`
645			`read-write`
646
647
648
649			`mc_reg`
650			`0x4`
651			`5`
652			`read-write`
653
654
655
656			`ls_reg`
657			`0x5`
658			`8`
659			`read-only`
660
661
662
663			`ms_reg`
664			`0x6`
665			`8`
666			`read-only`
667
668
669
670			`sr_reg`
671			`0x7`
672			`8`
673			`read-write`
674
675
676
677
678			`debug_0_reg`
679			`0x8`
680			`32`
681			`read-only`
682
683
684
685
686			`debug_1_reg`
687			`0xc`
688			`32`
689			`read-only`
690
691
692
693
694
695
696
697
698
699
700
701
702
703