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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_big  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   big
   8
     
     
 
        
         adr
         
         wb_adr_i
           71
         
       
 
 
        
         wdata
         
         wb_dat_i
           150
         
       
 
 
        
         rdata
         
         wb_dat_o
           150
         
       
 
 
        
         sel
         
         wb_sel_i
           10
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      wb_uart16550_bus16_big
    
  

 
 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_big
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_big
        verilogSourcemodule
      
 
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
    
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 

 

8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  16
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_big.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_big default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`big`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`71`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`150`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`150`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`10`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169	133	jt_eaton
170
171
172
173	131	jt_eaton	`gen_registers`
174	133	jt_eaton	`102.1`
175	131	jt_eaton	`none`
176			`common`
177			`./tools/regtool/gen_registers`
178
179
180			`bus_intf`
181			`wb`
182
183
184			`dest_dir`
185			`../verilog`
186
187
188
189
190
191
192
193
194			`gen_verilog`
195			`104.0`
196			`none`
197			`common`
198			`./tools/verilog/gen_verilog`
199
200
201			`destination`
202	134	jt_eaton	`wb_uart16550_bus16_big`
203	131	jt_eaton
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218			`fs-common`
219
220
221
222			`../verilog/top.body`
223			`verilogSourcefragment`
224
225
226
227
228
229
230
231
232
233			`fs-sim`
234
235
236
237			`../verilog/copyright.v`
238			`verilogSourceinclude`
239
240
241
242
243
244	134	jt_eaton	`../verilog/common/wb_uart16550_bus16_big`
245	131	jt_eaton	`verilogSourcemodule`
246
247
248
249
250
251			`../verilog/defines`
252			`verilogSourceinclude`
253
254
255
256			`wb`
257			`../verilog/wb_uart16550_bus16_big_wb`
258			`verilogSourcemodule`
259
260
261
262
263			`raminfr`
264			`../verilog/raminfr`
265			`verilogSourcemodule`
266
267
268
269			`receiver`
270			`../verilog/receiver`
271			`verilogSourcemodule`
272
273
274
275			`regs`
276			`../verilog/regs`
277			`verilogSourcemodule`
278
279
280
281			`rfifo`
282			`../verilog/rfifo`
283			`verilogSourcemodule`
284
285
286
287			`sync_flops`
288			`../verilog/sync_flops`
289			`verilogSourcemodule`
290
291
292
293			`tfifo`
294			`../verilog/tfifo`
295			`verilogSourcemodule`
296
297
298
299			`transmitter`
300			`../verilog/transmitter`
301			`verilogSourcemodule`
302
303
304
305			`wb_fsm`
306			`../verilog/wb_fsm`
307			`verilogSourcemodule`
308
309
310
311			`dest_dir../views/sim/`
312			`verilogSourcelibraryDir`
313
314
315
316
317
318
319
320
321			`fs-syn`
322
323
324
325			`../verilog/copyright.v`
326			`verilogSourceinclude`
327
328
329
330
331
332	134	jt_eaton	`../verilog/common/wb_uart16550_bus16_big`
333	131	jt_eaton	`verilogSourcemodule`
334
335
336
337
338
339
340
341			`../verilog/defines`
342			`verilogSourceinclude`
343
344
345
346			`wb`
347			`../verilog/wb_uart16550_bus16_big_wb`
348			`verilogSourcemodule`
349
350
351
352
353			`raminfr`
354			`../verilog/raminfr`
355			`verilogSourcemodule`
356
357
358
359			`receiver`
360			`../verilog/receiver`
361			`verilogSourcemodule`
362
363
364
365			`regs`
366			`../verilog/regs`
367			`verilogSourcemodule`
368
369
370
371			`rfifo`
372			`../verilog/rfifo`
373			`verilogSourcemodule`
374
375
376
377			`sync_flops`
378			`../verilog/sync_flops`
379			`verilogSourcemodule`
380
381
382
383			`tfifo`
384			`../verilog/tfifo`
385			`verilogSourcemodule`
386
387
388
389			`transmitter`
390			`../verilog/transmitter`
391			`verilogSourcemodule`
392
393
394
395			`wb_fsm`
396			`../verilog/wb_fsm`
397			`verilogSourcemodule`
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414			`verilog`
415
416
417			`spirit:library="Testbench"`
418			`spirit:name="toolflow"`
419			`spirit:version="verilog"/>`
420
421
422
423
424
425
426
427
428
429			`commoncommon`
430
431			`Verilog`
432
433
434			`fs-common`
435
436
437
438
439			`sim:Simulation:`
440
441			`Verilog`
442
443
444			`fs-sim`
445
446
447
448
449			`syn:Synthesis:`
450
451			`Verilog`
452
453
454			`fs-syn`
455
456
457
458
459
460			`doc`
461
462
463			`spirit:library="Testbench"`
464			`spirit:name="toolflow"`
465			`spirit:version="documentation"/>`
466
467			`:Documentation:`
468			`Verilog`
469
470
471
472
473
474
475
476
477
478			`baud_o`
479			`wire`
480			`out`
481
482
483			`cts_pad_i`
484			`wire`
485			`in`
486
487
488			`dcd_pad_i`
489			`wire`
490			`in`
491
492
493			`dsr_pad_i`
494			`wire`
495			`in`
496
497
498			`dtr_pad_o`
499			`wire`
500			`out`
501
502
503			`int_o`
504			`wire`
505			`out`
506
507
508
509			`ri_pad_i`
510			`wire`
511			`in`
512
513
514			`rts_pad_o`
515			`wire`
516			`out`
517
518
519			`srx_pad_i`
520			`wire`
521			`in`
522
523
524			`stx_pad_o`
525			`wire`
526			`out`
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541			`8`
542			`wb`
543
544			`wb`
545			`0x00`
546
547
548			`mb_microbus`
549			`0x100`
550			`16`
551
552
553
554			`rb_dll_reg`
555			`0x0`
556			`8`
557			`read-only`
558
559
560
561			`tr_reg`
562			`0x0`
563			`8`
564			`write-strobe`
565
566
567
568
569			`ie_dlh_reg`
570			`0x1`
571			`8`
572			`read-only`
573
574
575
576			`ie_reg`
577			`0x1`
578			`4`
579			`write-strobe`
580
581
582
583
584			`dll_reg`
585			`0x0`
586			`8`
587			`write-strobe`
588
589
590
591
592			`dlh_reg`
593			`0x1`
594			`8`
595			`write-strobe`
596
597
598
599
600
601			`ii_reg`
602			`0x2`
603			`4`
604			`read-only`
605
606
607
608			`fc_reg`
609			`0x2`
610			`8`
611			`write-only`
612
613
614
615
616			`lc_reg`
617			`0x3`
618			`8`
619			`read-write`
620
621
622
623			`mc_reg`
624			`0x4`
625			`5`
626			`read-write`
627
628
629
630			`ls_reg`
631			`0x5`
632			`8`
633			`read-only`
634
635
636
637			`ms_reg`
638			`0x6`
639			`8`
640			`read-only`
641
642
643
644			`sr_reg`
645			`0x7`
646			`8`
647			`read-write`
648
649
650
651
652			`debug_0_reg`
653			`0x8`
654			`32`
655			`read-only`
656
657
658
659
660			`debug_1_reg`
661			`0xc`
662			`32`
663			`read-only`
664
665
666
667
668
669
670
671
672
673
674
675
676
677