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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_big.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_big  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   big
   8
        
     
 
        
         adr
         
         wb_adr_i
           72
         
       
 
 
        
         wdata
         
         wb_dat_i
           310
         
       
 
 
        
         rdata
         
         wb_dat_o
           310
         
       
 
 
        
         sel
         
         wb_sel_i
           30
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.bus32_big
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
  
 
 
 
 
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_big
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_big_wb
        verilogSourcemodule
      
 
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus32_big
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width32
wb_byte_lanes4
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 


8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  32
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 

   debug_0_reg
   0x8
   32
   read-only
  
 
 

   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_big.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_big default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`big`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`72`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`310`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`310`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`30`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170	133	jt_eaton
171
172	131	jt_eaton
173	133	jt_eaton	`elab_verilog`
174			`102.1`
175			`none`
176			`:Simulation:`
177			`./tools/verilog/elab_verilog`
178
179
180			`dest_dir`
181			`io_ports`
182
183
184
185
186
187
188
189
190
191
192	131	jt_eaton	`gen_registers`
193	133	jt_eaton	`102.1`
194	131	jt_eaton	`none`
195			`common`
196			`./tools/regtool/gen_registers`
197
198
199			`bus_intf`
200			`wb`
201
202
203			`dest_dir`
204			`../verilog`
205
206
207
208
209
210
211
212
213			`gen_verilog`
214			`104.0`
215			`none`
216			`common`
217			`./tools/verilog/gen_verilog`
218
219
220			`destination`
221			`top.bus32_big`
222
223
224			`dest_dir`
225			`../verilog`
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246			`fs-common`
247
248
249
250			`../verilog/top.body`
251			`verilogSourcefragment`
252
253
254
255
256
257
258
259
260
261
262
263			`fs-sim`
264
265
266
267			`../verilog/copyright.v`
268			`verilogSourceinclude`
269
270
271
272
273			`../verilog/common/top.bus32_big`
274			`verilogSourcemodule`
275
276
277
278
279
280
281			`../verilog/defines`
282			`verilogSourceinclude`
283
284
285
286			`wb`
287			`../verilog/wb_uart16550_bus32_big_wb`
288			`verilogSourcemodule`
289
290
291
292
293
294			`raminfr`
295			`../verilog/raminfr`
296			`verilogSourcemodule`
297
298
299
300			`receiver`
301			`../verilog/receiver`
302			`verilogSourcemodule`
303
304
305
306			`regs`
307			`../verilog/regs`
308			`verilogSourcemodule`
309
310
311
312			`rfifo`
313			`../verilog/rfifo`
314			`verilogSourcemodule`
315
316
317
318			`sync_flops`
319			`../verilog/sync_flops`
320			`verilogSourcemodule`
321
322
323
324			`tfifo`
325			`../verilog/tfifo`
326			`verilogSourcemodule`
327
328
329
330			`transmitter`
331			`../verilog/transmitter`
332			`verilogSourcemodule`
333
334
335
336			`wb_fsm`
337			`../verilog/wb_fsm`
338			`verilogSourcemodule`
339
340
341
342
343
344
345
346
347
348			`fs-syn`
349
350
351
352			`../verilog/copyright.v`
353			`verilogSourceinclude`
354
355
356
357
358
359			`../verilog/common/top.bus32_big`
360			`verilogSourcemodule`
361
362
363
364
365
366			`../verilog/defines`
367			`verilogSourceinclude`
368
369
370
371			`wb`
372			`../verilog/wb_uart16550_bus32_big_wb`
373			`verilogSourcemodule`
374
375
376
377
378			`raminfr`
379			`../verilog/raminfr`
380			`verilogSourcemodule`
381
382
383
384			`receiver`
385			`../verilog/receiver`
386			`verilogSourcemodule`
387
388
389
390			`regs`
391			`../verilog/regs`
392			`verilogSourcemodule`
393
394
395
396			`rfifo`
397			`../verilog/rfifo`
398			`verilogSourcemodule`
399
400
401
402			`sync_flops`
403			`../verilog/sync_flops`
404			`verilogSourcemodule`
405
406
407
408			`tfifo`
409			`../verilog/tfifo`
410			`verilogSourcemodule`
411
412
413
414			`transmitter`
415			`../verilog/transmitter`
416			`verilogSourcemodule`
417
418
419
420			`wb_fsm`
421			`../verilog/wb_fsm`
422			`verilogSourcemodule`
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441			`verilog`
442
443
444			`spirit:library="Testbench"`
445			`spirit:name="toolflow"`
446			`spirit:version="verilog"/>`
447
448
449
450
451
452
453
454
455			`commoncommon`
456
457			`Verilog`
458
459
460			`fs-common`
461
462
463
464
465
466			`sim:Simulation:`
467
468			`Verilog`
469
470
471			`fs-sim`
472
473
474
475
476			`syn:Synthesis:`
477
478			`Verilog`
479
480
481			`fs-syn`
482
483
484
485
486
487			`doc`
488
489
490			`spirit:library="Testbench"`
491			`spirit:name="toolflow"`
492			`spirit:version="documentation"/>`
493
494			`:Documentation:`
495			`Verilog`
496
497
498
499
500
501
502
503
504			`wb_addr_width8`
505			`wb_data_width32`
506			`wb_byte_lanes4`
507			`PRESCALER_PRESET16'h1234`
508
509
510
511
512
513			`baud_o`
514			`wire`
515			`out`
516
517
518			`cts_pad_i`
519			`wire`
520			`in`
521
522
523			`dcd_pad_i`
524			`wire`
525			`in`
526
527
528			`dsr_pad_i`
529			`wire`
530			`in`
531
532
533			`dtr_pad_o`
534			`wire`
535			`out`
536
537
538			`int_o`
539			`wire`
540			`out`
541
542
543
544			`ri_pad_i`
545			`wire`
546			`in`
547
548
549			`rts_pad_o`
550			`wire`
551			`out`
552
553
554			`srx_pad_i`
555			`wire`
556			`in`
557
558
559			`stx_pad_o`
560			`wire`
561			`out`
562
563
564
565
566
567
568
569
570
571
572
573
574
575			`8`
576			`wb`
577
578			`wb`
579			`0x00`
580
581
582			`mb_microbus`
583			`0x100`
584			`32`
585
586
587
588			`rb_dll_reg`
589			`0x0`
590			`8`
591			`read-only`
592
593
594
595			`tr_reg`
596			`0x0`
597			`8`
598			`write-strobe`
599
600
601
602
603			`ie_dlh_reg`
604			`0x1`
605			`8`
606			`read-only`
607
608
609
610			`ie_reg`
611			`0x1`
612			`4`
613			`write-strobe`
614
615
616
617
618			`dll_reg`
619			`0x0`
620			`8`
621			`write-strobe`
622
623
624
625
626			`dlh_reg`
627			`0x1`
628			`8`
629			`write-strobe`
630
631
632
633
634
635
636			`ii_reg`
637			`0x2`
638			`4`
639			`read-only`
640
641
642
643			`fc_reg`
644			`0x2`
645			`8`
646			`write-only`
647
648
649
650			`lc_reg`
651			`0x3`
652			`8`
653			`read-write`
654
655
656
657			`mc_reg`
658			`0x4`
659			`5`
660			`read-write`
661
662
663
664			`ls_reg`
665			`0x5`
666			`8`
667			`read-only`
668
669
670
671			`ms_reg`
672			`0x6`
673			`8`
674			`read-only`
675
676
677
678			`sr_reg`
679			`0x7`
680			`8`
681			`read-write`
682
683
684
685
686
687			`debug_0_reg`
688			`0x8`
689			`32`
690			`read-only`
691
692
693
694
695			`debug_1_reg`
696			`0xc`
697			`32`
698			`read-only`
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720